Xilinx SP701 User Manual page 18

Spartan-7
FPGA
For more details, see the Micron MT41K256M16TW-107 data sheet at the
website.
The detailed FPGA connections for the feature described in this section are documented in the
SP701 board XDC file, referenced in
information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions (UG586).
Quad SPI Flash Memory
[Figure 2, callout 2]
A single Micron MT25QL01GBBBESF-0SIT 1 Gb serial NOR Flash memory (U3) holds the boot
images for the XC7S100 device. The Spartan-7 configuration clock is 66 MHz resulting in a
typical configuration time of 112 ms. This memory can also be used for user data.
UG1319 (v1.0) July 12, 2019
SP701 Board User Guide
Figure 4: DDR3L Memory Interface
U1
VDDO_34
VDDO_34
VDDO_34
A[14:0]
DQ[7:0]
UDM
UDQS/UDQS#
DQ[15:8]
LDM
LDQS/LDQS#
CK/CK#
CKE
BA[2:0]
ODT
RAS#, CAS#, WE#
RESET#
Appendix B: Xilinx Design
Chapter 3: Board Component Descriptions
1.35V
1.35V
1.35V
0.675V
0.675V
CS#
100E
240E
Constraints. For more
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U12
VDD
VDDQ
VREFCA
DDR3L SDRAM
MT41K256M16TW-
107cc
VREFDQ
ZQ
X22787-042619
Micron Technology
www.xilinx.com
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