Xilinx SP701 User Manual page 33

The detailed FPGA connections for the feature described in this section are documented in the
SP701 board XDC file, referenced in
User PMOD GPIO Connectors
[Figure 2, callout 20, 21]
The SP701 evaluation board implements six right-angle PMOD GPIO receptacles J14-J19. The
3.3V PMOD nets are wired to the XC7S100 FPGA 3.3V bank 16. For more information about
PMOD connector compatible PMOD modules, see the
The following figure shows the GPIO PMOD connectors.
UG1319 (v1.0) July 12, 2019
SP701 Board User Guide
Figure 16: User GPIO
Bank 15
Vcco = 3.3V
Bank 13
Vcco = 1.8V
Spartan-7 FPGA
Appendix B: Xilinx Design
Chapter 3: Board Component Descriptions
GPIOx8
1.8V
GPIOx8
1.8V
GPIOx8
1.8V
GPIOx5
1.8V
GPIOx1
Constraints.
Digilent Inc. website.
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