Xilinx SP701 User Manual page 24

The SP701 evaluation board uses dual TI PHY device DP83867IRPAP (U14, U16) for Ethernet
communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board only supports the RGMII
mode. Each PHY connects to a user-provided Ethernet cable through RJ-45 connector (J9, J11),
Wurth 7499111221A with built-in magnetics, and status LEDs. On power-up, or on reset, the
PHY are configured to operate in the RGMII mode with the PHY addresses set by hardware strap
settings:
• PHY1 U14 PHY_ADDR[4:0] = 0001
• PHY2 U16 PHY_ADDR[4:0] = 0010
The TI DP83867IRPAP data sheet is on the
The Ethernet PHY components have their own JTAG chain connected to 2x5 male pin header
J10 as shown in the following figure.
UG1319 (v1.0) July 12, 2019
SP701 Board User Guide
Figure 9: SP701 Dual Ethernet
RGMII
MDIO
Spartan-7
I2C
FPGA
RGMII
MDIO
Chapter 3: Board Component Descriptions
MII
DP83867IR
10/100/1000
PHY
25 MHz
Crystal
32 Kb
EEPROM
For EtherCAT
MII
DP83867IR
10/100/1000
PHY
25 MHz
Crystal
Texas Instruments website.
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