Xilinx SP701 User Manual page 42

Temperature
VP_0
VN_0
VAUXP[0]
VAUXN[0]
VAUXP[12]
VAUXN[12]
VAUXP[13]
External
VAUXN[13]
Analog
VAUXP[14]
Inputs
VAUXN[14]
VAUXP[15]
VAUXN[15]
It is not necessary to instantiate the XADC in a design to access the on-chip monitoring
capability. However, if the XADC is not instantiated in a design, the only way to access this
information is through the JTAG test access port (TAP). To allow access to the status registers
(measurement results) from the FPGA logic, the XADC must be instantiated.
The following figure shows the SYSMON implementation and SYSMON header J24, a 2x10
shrouded male pin header. Jumper J26 is provided to select internal reference or external
reference.
UG1319 (v1.0) July 12, 2019
SP701 Board User Guide
Figure 23: XADC (SYSMON) Block Diagram
Supply
Temperature
VCCINT
Sensor Sensors
VCCAUX
VCCBRAM
Die
VCCPINT
°C
VCCPAUX
VCCO_DDR
Mux
Mux
Chapter 3: Board Component Descriptions
VREP_0 VREFN_0
On-Chip Ref
1.25V
Control
12-bit, Registers
1 MSPS
ADC A
64 x 16 bits
Read/Write
12-bit,
1 MSPS
ADC B
JTAG
Send Feedback
Status
Registers
64 x 16 bits
Read Only
DRP
FPGA
Interconnect
X17015-070719
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