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Operation
3.16 Pattern Generator
3.16.1
Library of Patterns
3.16.2
Programmable Patterns
48
The pattern generator utilizes a half rate clock architecture that enables
patterns to be generated at data rates from 5 to 32 Gb/s or
4 to 17 Gb/s. The differential output has fully adjustable output
amplitude, crossover, termination, and DC offset.
All features can be controlled through the control panel on the front
panel of the N4960A serial BERT controller, remote SCPI commands, or
through the N4980A multi-instrument BERT software.
Provided with the pattern generator is a large library of common stress
patterns:
•
Family of hardware generated PRBS patterns (2n – 1, n = 7, 9, 10,
11, 15, 23, 29, 31, 33, 35, 39, 41, 45, 47, 49, 51)
•
Clock patterns (÷2, ÷4, ÷8,..., ÷64)
•
K28 series patterns (K28.3, K28.5, K28.7)
•
CJ series patterns (CJPAT, CJTPAT, CRPAT)
•
JSPAT and JTSPAT patterns
Pattern inversion is available for all patterns.
The pattern generator allows custom designed patterns from 1 bit – 8
Mbit memory depth to be created and uploaded to meet application
requirements. User patterns must fit into the internal 512-bit memory
boundary; therefore, all odd-length patterns will be replicated 512 times
before loading into the N4960A, and even-length patterns will be
replicated between 1 and 256 times (depending on the actual length of
the pattern). Patterns are created and loaded into the N4960A Serial
BERT using the N4980A Multi-instrument BERT Software package; the
pattern editor in this software performs the necessary replication
calculations and will advise the user of any patterns that will not fit into
the 8 Mb memory (after replication) along with suggestions on the
nearest pattern lengths that will fit.
Keysight N4960A Serial BERT 17 and 32 Gb/s User Guide
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