Keysight Technologies N4960A User Manual page 28

Operation
Item
Clock outputs
Jitter
Delay
Divided
28
Description
The jitter output is the main stressed clock output. The clock phase can be
modulated in time with one or more calibrated jitter sources. The output
amplitude, offset, and termination voltage are also user settable.
The jitter sources are:
•
Sinusoidal jitter 1 (SJ1)
•
Sinusoidal jitter 2 (SJ2) (N4960A-CJ1 only)
•
Sinusoidal periodic jitter (PJ)
•
Externally supplied jitter
•
Random jitter (RJ) is internally sourced (N4960A-CJ1 only)
Sinusoidal jitter 1, Sinusoidal jitter 2, random jitter, and external jitter (high
frequency band) can be enabled simultaneously. However, the sum of these
paths must be kept below the specified maximum modulation level. In
addition, the periodic jitter path or external low band (high deviation) jitter
path cannot be enabled if any of the other jitter paths are enabled.
By disabling the stress sources, this output can be used to provide a clean
(non-jittered) clock.
The jitter output also provides the clock source for the pattern generator.
When used as a BERT, the synthesizer clock frequency is set to 1/2 of the
BERT data rate. Any stress applied to the jitter clock output will appear on the
pattern generator output (channel 0 only) at 2x the amplitude of the clock
jitter.
The delay differential output provides a non-stressed clock output with
adjustable phase offset (in UI) as well as amplitude, offset, and termination
voltage adjustment.
The delay clock is also used to clock the error detector. When operating as a
BERT, both auto and manual detector alignment will alter the delay setting for
the front panel output. Conversely, manually setting the delay output delay
value may degrade the error detector operation by misaligning the detector
sample point. The value of delay applied to the delay clock output will appear
on the error detector or pattern generator output (channel 1 only) at 2x the
value of the clock delay.
The divided differential clock output produces a non-stressed signal that is
related to the clock frequency by a divider factor. The divided clock output
signal also has amplitude, offset, and termination voltage adjustment.
By setting the divide ratio to 1, this output can be used as a non-divided clean
(non-jittered) clock.
Keysight N4960A Serial BERT 17 and 32 Gb/s User Guide