Table of Contents
Advertisement
Operation
3.15 N4960A Serial BERT Controller
3.15.1
Divided Clock Output
40
The N4960A serial BERT controller has the capability to divide the clock
frequency over a broad range of divide ratios and return the divided
signal as fully differential non-stressed outputs with adjustable
amplitude and offset. This provides the user a convenient method for
generating a trigger signal to use with a scope, or other applications
requiring a sub rate clock.
The divide ratios are 1 to 99,999,999 with no missing integers. The
divided clock settings can be controlled programmatically or through
the front panel.
The divided clock output duty cycle varies between 33% and 66% as a
function of the divide ratio, N. When N is a power of two, the duty cycle
is exactly 50%. As N deviates from a power of two, the duty cycle
deviates from 50%. For example, N=64 has 50% duty cycle, N=60 has
47% duty cycle, and N=56 has 43% duty cycle.
formulas for calculating pulse width and duty cycle as a function of N,
for any integer N from 2 to 99,999,999. The duty cycle of the divided
clock is 50% ± 10% when the divide ratio is set to 1.
Figure 18. Calculating pulse width and duty cycle
Figure 19
is a plot of the duty cycle versus the divide ratio for N = 2 to
1024.
Figure 18
Keysight N4960A Serial BERT 17 and 32 Gb/s User Guide
shows the
Advertisement
Table of Contents
