Figure 5-6. Mixed Clock Demultiplexing - HP 64700 Series User Manual

mixed When the slave clock mode is "mixed", the lower
eight external bits (0-7) are latched when the
slave clock (as specified by your answers to the
next four questions) is received. The upper eight
bits and the latched lower eight are then clocked
into the analyzer when the emulation clock is
received (see figure 5-6).

Figure 5-6. Mixed Clock Demultiplexing

If no slave clock has appeared since the last
master clock, the data on the lower 8 bits of the
pod will be latched at the same time as the upper
8 bits. If more than one slave clock has appeared
since the last master clock, only the first slave
data will be available to the analyzer (see figure
5-7).
5-10 Using the External Analyzer