Block Diagram Description; Clock. Start. And Stop Signal Paths; Scanaest Oscillator (Internal Clock); Self-Test - HP 5004A Operating And Service Manual

Model 5004A
Service
8-50.

BLOCK DIAGRAM DESCRIPTION

8-51. In the following paragraphs a description of the 5004A Signature Analyzer i s given to
match Figure 8-3 the block diagram in this section. A more detailed description of the 5004A
is given in the paragraphs following the heading: CIRCUIT THEORY (PRINCIPLES OF OPER-
ATION) (SCHEMATIC DIAGRAM DESCRIPTION).
8-52. A 5004A Signature Analyzer requires four input signals: START, STOP, CLOCK, and
DATA. START, CLOCK, and STOP inputs are applied to the 5004A through the GATING SIG-
NALS POD.
Data Signal Path. DATA input is through the DATA PROBE. Signals applied to the
8-53.
DATA PROBE are connected to dual paths which trigger at high and low voltage levels respec-
tively. The output of these level detectors i s at ECL level and drive a pair of ECL to TTL con-
verters on the main assembly. A logic level detector across the ECL converters provides the
drive for the logic level indicator at the data probe tip. The outputs of the ECL converters is
translated from a possible three levels (high, bad (middle), and low) to standard high or low
levels at the selected clock. (When a bad level appears at the input of the data probe, it is con-
verted to whatever the previous data level was: (either high or low.) Data from the 3-to-2 level
converter is applied to the pseudo-random word generator with corresponding gate and clock
signals. For each different clocked data stream (series of bits) bracketed by a start and stop
signal, a different word (signature) is generated by the word generator. Each signature i s sent
to the display latches which supply them to the decoder-driver and the signature comparator.
The decoder-driver translates the signature to a special-form hexadecimal number which is
applied to the display. Each succeeding signature is compared with the preceding signature
in the signature comparator which will activate the UNSTABLE SIGNATURE lamp if two suc-
ceeding signatures are different. The R E S E T function for the entire 5004A i s part of the DATA
probe. R E S E T is activated by a switch (labeled RESET) on the DATA probe.
8-54. Clock, Start, and Stop Signal Paths
8-55. External CLOCK, START, and STOP signals are applied to the 5004A through the gating
signals pod. Input CLOCK, START, and STOP signals are eamplified, and connected to operator-
controlled edge-select circuits. After edge-selection the CLOCK, START, and STOP signals are
combined to form a gating (gate) control signal. (The external CLOCK signal is also buffered
and used to time other sections of the 5004A.) The gate signal is presented on the front panel
with a GATE indicator lamp. The gate signal is for on-off (start-stop) control of the word
generator.
8-56.
8-57. A kilohertz signals i s generated in the 5004A for display scan and test use. The scan
signal controls switching the displays on and off (fast enough to be not noticeable) to lower
power consumption and reduce the size of drive circuit components. In the SELF-TEST and
the external clock normally applied to the gating signals pod.
8-58. Self -Test
8-57. Part of the 5004A is a circuit used only for self-test of the signature analyzer. The self-
test function is controlled by a front panel switch. In the self-test mode special signatures are
generated using the internal test signal frequency divider output (ROM). If there is a defect in
the 5004A the self-test signature will not be correct.