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HP 64700 series User Manual

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HP 64700 Series Emulators
Analyzer
PC Interface
User's Guide
HP Part No. 64740-97007
Printed in U.S.A.
August 1990
Edition 4

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  • Page 1 HP 64700 Series Emulators Analyzer PC Interface User’s Guide HP Part No. 64740-97007 Printed in U.S.A. August 1990 Edition 4...
  • Page 3 Hewlett-Packard Company. The information contained in this document is subject to change without notice. Advancelink, Vectra, and HP are trademarks of Hewlett-Packard Company. IBM and PC AT are registered trademarks of International Business Machines Corporation.
  • Page 4 Printing History New editions are complete revisions of the manual. The date on the title page changes only when a new edition is published. A software code may be printed before the date; this indicates the version level of the software product at the time the manual was issued. Many product updates and fixes do not require manual changes, and manual corrections may be done without accompanying product changes.

  • Page 5: Using This Manual

    Using this Manual This manual will show you how to use the HP 64700 series analyzer with the host computer PC Interface. This manual will: Briefly introduce the analyzer and its features. Show you how to use the analyzer in its simplest, power-up condition.
  • Page 6 Organization Chapter 1 Introducing the HP 64700 Series Analyzer. This chapter lists the basic features of the analyzer. The following chapters show you how to use these features. Chapter 2 Using the Internal Analyzer. This chapter shows you how to use the internal emulation analyzer, and it describes the basic steps performed when using the analyzer.

  • Page 7: Table Of Contents

    Contents Introducing the HP 64700 Series Analyzer Overview ....... 1-1 Analyzer Features .
  • Page 8 Resetting the Trace Specification ....2-13 Starting the Trace ......2-13 Halting a Trace Measurement .
  • Page 9 Using the External State Analyzer ....4-14 Selecting the Clock Source ....4-14 Specifying the Maximum Qualified Clock Speed .
  • Page 10 Magnify About (X or O) ....5-18 Inserting/Deleting Channels ....5-19 Examples .
  • Page 11 Illustrations Figure 1-1. Block Diagram of HP 64700 Series Analyzer ..1-2 Figure 2-1. Trace Specification Screen ....2-2 Figure 2-2. Ranges, Patterns, and Expressions ... 2-8 Figure 2-3.
  • Page 12 Figure 5-4. Standard Acquisition Mode ....5-8 Figure 5-5. Glitch Acquisition Mode ....5-8 Figure 5-6.

  • Page 13: Introducing The Hp 64700 Series Analyzer

    Introducing the HP 64700 Series Analyzer Overview This manual describes the HP 64700 Series analyzer. Each HP 64700 Series emulator contains an internal emulation analyzer. Some emulators may optionally contain an external analyzer. The emulation analyzer, also known as the internal analyzer, captures emulator bus cycle information synchronously with the processor’s...

  • Page 14: Figure 1-1. Block Diagram Of Hp 64700 Series Analyzer

    Figure 1-1. Block Diagram of HP 64700 Series Analyzer 1-2 Introduction...

  • Page 15: Analyzer Features

    Analyzer Features This chapter lists basic features of the HP 64700 Series analyzer. The chapters which follow show you how to use these features. Simple Measurements The default condition of the analyzer allows you to perform a simple measurement by entering a single "analysis begin" command. You can enter additional trace commands to qualify when execution should be traced and which bus cycle states should be stored.

  • Page 16: External Timing Analysis

    External Timing If your emulator contains an external analyzer, you can configure the external analyzer to perform timing measurements. Some of the Analysis features of the external timing analyzer are listed below. Standard data acquisition mode with a maximum sample rate of 100 MHz (10 ns).

  • Page 17: Coordinated Measurements

    Coordinated When multiple HP 64700 Series emulators are connected via the Coordinated Measurement Bus (CMB), you can use the analyzer to Measurements trigger the analyzers of other emulators. You can also use the analyzer to trigger instruments connected to the BNC port. Conversely, the analyzer may be triggered by other emulators and instruments.
  • Page 18 Notes 1-6 Introduction...

  • Page 19: Using The Internal Analyzer

    Using the Internal Analyzer Introduction This chapter describes how to use the emulation analyzer from within the PC Interface. The steps performed when using the analyzer are: Modifying the trace specification (or using the default). Starting the trace. Displaying the trace. These steps are described in the main sections of this chapter.

  • Page 20: Sequence Levels

    the secondary branch mode, the count and prestore qualifiers, and the trigger position selection. When you initially enter the PC Interface, the default analyzer configuration specifies a trigger on any state, and that all captured states are stored. Sequence Levels The trace specification screen in figure 2-1 shows two sequence levels.

  • Page 21: Sequence Level Field

    One of the sequence levels is specified as the trigger level. The analyzer triggers when it finds the state associated with this level. The trigger is the reference point in the resulting trace. States are stored before, after, or about the trigger state. The trigger state is always on line 0 of the trace.

  • Page 22: Storage Qualifier Field

    Now try to delete the trigger level. Notice that the following level is made the trigger level until it is the second to last; then, the previous level is made the trigger level. Storage Qualifier Field The storage qualifier field allows you to specify which states are stored while the analyzer searches for that sequence level’s find or trigger state.

  • Page 23: Occurrence Count Field

    Occurrence Count Field The occurrence count field specifies the number of times the state specified in the find/trigger field must be found before the analyzer goes on to the following sequence level. The default base for an occurrence count is decimal. You may specify occurrence counts from 1 to 65535.

  • Page 24: Count

    No branch state qualifier field is added to the last sequence level, but you are given a field in which to specify the sequence level the analyzer branches to when the "then find" state is found. Count For each stored state, the analyzer can either count time or the number of occurrences of some state.

  • Page 25: Trigger Position

    Trigger Position The trigger position specifies where the trigger state appears in the trace. center Use "center" when you are interested in states that occur before and after the trigger. Use "end" when you are only interested in states that occur before the trigger. start Use "start"...

  • Page 26: Constants

    Figure 2-2. Ranges, Patterns, and Expressions number bases (including predefined equates in the status field only). You can also use operators to combine symbols and numeric constants. Constants. Values may be specified as numeric constants in hexadecimal, decimal, octal, or binary. The number bases are specified by the following characters: Binary (example: 10010110y).

  • Page 27: Operators

    all don’t cares may be represented by a question mark (?) or a blank field. Operators. Values can also be symbols and numeric constants combined with operators. All operations are carried out on 32-bit, two’s complement integers. (Values which are not 32 bits will be sign extended when expression evaluation occurs.) The available operators are listed below in descending order of evaluation precedence.

  • Page 28: Assigning Values To The Range Resource

    5FFH AND data equal to 1234H in order to match the pattern. Trace Labels. The following trace labels are predefined in most of the HP 64700 Series emulators: addr Represents the trace signals which monitor the emulation processor’s address pins (trace signals 0 through 23 in the 68000 emulator).

  • Page 29: Predefined Values For 68000 Emulator Status

    data Represents the trace signals which monitor the emulation processor’s data pins (trace signals 32 through 47 in the 68000 emulator). stat Represents the trace signals which monitor other emulation processor signals (trace signals 24 through 31 in the 68000 emulator). xbits Represents the external trace signals.

  • Page 30: Specifying Pattern Expressions

    You can also select these predefined values when specifying status values for the pattern resources. The predefined values for emulator status are different for each emulator. Refer to your PC Interface: Emulator User’s Guide for the definitions of the status values predefined for your emulator. Specifying Pattern Expressions The range and pattern resources and the arm condition are split into two sets.

  • Page 31: Set Operator Limitations

    Set Operator Limitations. Only the OR (|) and NOR (~) logical operators are available as intraset operators. However, you can create the AND and NAND operators by applying DeMorgan’s law: a AND b = a ~ b a NAND b = a | b To create a logical NOT of a pattern resource, invert the equality used when assigning values to that resource.

  • Page 32: Halting A Trace Measurement

    states that can be displayed is shown at the bottom of the screen. If there are states to display, then situation 1 above has occurred. If there are no states to display, then situation 2 above has occurred. If the trigger state has not been found and you think it should have been found, you may want to halt the trace and review your trace specification.
  • Page 33 The first column on the trace list contains the line number. The trigger is always on line 0. The second column contains the address information associated with the trace states. Addresses in this column may be locations of instruction opcodes on fetch cycles, or they may be sources or destinations of operand cycles.

  • Page 34: Changing The Trace Format

    The last column contains information about the sequencer. The "+" on line 0 indicates the state caused a sequencer branch (in this case, the trigger on any state). Sometimes, the trace will show opcode fetches for instructions which are not executed because of a transfer of execution to other addresses. This can happen with microprocessors like the 68000 and the 80186 because they have pipelined architectures or instruction queues which allow them to prefetch the next few instructions before the current...

  • Page 35: Trace Labels

    Figure 2-3. Analysis Format Screen Trace Labels The bottom part of the "Analysis Format" display is used to specify which trace labels appear in which column of the display. Several trace labels are predefined for the internal emulation analyzer. You can specify the number base (in hexadecimal, binary, octal, decimal, and ASCII) for several of the predefined trace labels.
  • Page 36 Captured information disassembled and presented in mnemonic format. count State or time count information presented in absolute format (relative to the trigger state) or relative format (relative to the previous state in the trace). Shows a "+" if the captured state is one the analyzer was searching for and found (in other words, a find state, a trigger state, or an branch state).

  • Page 37: Internal Analyzer Examples

    Internal Analyzer Examples Introduction This chapter shows you how to use the emulation analyzer from within the PC Interface. It shows you how to make simple measurements as well as how to search for a sequence of states. This chapter describes: The sample program on which example measurements are made.

  • Page 38: Prerequisites

    The sample program is used to illustrate analyzer examples. The examples in this chapter have been generated using an 68000 Program (HP 64742) emulator. The sample program is written in 68000 assembly language. It is not important that you know the 68000 assembly language;...

  • Page 39: Figure 3-1. Pseudo-Code Algorithm Of Sample Program

    Initialize the stack pointer. Set up number counter. AGAIN: Save the two previous random numbers. Call the RAND random number generator subroutine. Test the two least significant bits of the previous random number. If 00B then goto CALLER_0. If 01B then goto CALLER_1. If 10B then goto CALLER_2.

  • Page 40: Figure 3-2. Sample Program Listing

    HEWLETT-PACKARD: 68000 Assembler FILE: C:\MNL\ODY\ANLY\PCI\SRC\68K\SRND.S LOCATION OBJECT CODE LINE SOURCE LINE 1 "68000" 2 ************************************************** 3 * The "srnd.S" program runs in an infinite loop, 4 * writing random numbers to an output area and 5 * sorting the output area after 4FFH random 6 * numbers have been written.
  • Page 41 000446 0C42 0000 53 TEST CMPI #0,D2 54 ;------------------------------------------------- 55 ; If the counter is not zero, continue to write 56 ; random numbers. 57 ;------------------------------------------------- 00044A 57CA FFBE DBEQ D2,AGAIN 59 ;------------------------------------------------- 60 ; The counter is zero. Sort the random numbers 61 ;...
  • Page 42 103 * The QSORT subroutine is passed (on the stack) 104 * the high and low addresses of an area of bytes 105 * to be sorted. 106 ************************************************** 000494 226F 0008 107 QSORT MOVE.L 8[A7],A1 ; A1 = high index. 000498 206F 0004 MOVE.L 4[A7],A0...
  • Page 43 159 ;------------------------------------------------- 160 ; A0 = low address (needed to swap dividing value). 161 ;------------------------------------------------- 0004CA 206F 0004 162 OUT MOVE.L 4[A7],A0) 163 ;------------------------------------------------- 164 ; Swap dividing value and high index value. 165 ;------------------------------------------------- 0004CE 1091 MOVE.B [A1],[A0] 0004D0 1282 MOVE.B D2,[A1] 168 ;-------------------------------------------------...

  • Page 44: Mapping Memory For The Sample Program

    CALLER_2 CALLER_3 DEC_HIGH 134, DONE INC_LOW 137, 136, OVER QSORT 180, RAND RAND_SEED RESULTS STACK START TEST TWO_THREE WRITE_NUMBER ZERO_ONE Figure 3-2. Sample Program Listing (Cont’d) Mapping Memory for The program, destination, and stack areas of the sample program were ORGed at addresses 400H, 500H, and 600H, respectively.

  • Page 45: Loading The Sample Program

    Figure 3-3. Memory Map Configuration Display Loading the Sample If you have already assembled and linked the sample program, you can load the absolute file by selecting: Program Memory, Load Move the cursor to the "Format" field and select the appropriate format (HP64000 in this example).

  • Page 46: Set Up The Stack Pointer

    Set Up the Stack The 68000 emulator requires you to set up the system stack pointer before you can run the program. To set up the system stack pointer, Pointer you must first break into the monitor. Processor, Break To modify the system stack pointer, select: Register, Modify Use the Tab key to select register ssp, press Enter, type in the address 0BFEH, and press Enter once again.

  • Page 47: Specifying A Simple Trigger

    Specifying a Suppose you want to look at the execution of the sample program after the AGAIN address, but only after it has occurred three times (in other Simple Trigger words, after the program has executed its complete loop three times). To do this, select: Analysis, Trace, Modify Modify the trace specification as shown in figure 3-4.
  • Page 48 Figure 3-4. Simple Trigger Specification (Cont’d) To begin the trace, select: Analysis, Begin After the "Trace complete" message is shown on the status line, display the trace by selecting: Analysis, Display Type the first state that can be displayed into the starting state field and press Enter.
  • Page 49 In the trace list above, line 0 shows the beginning of the program loop and line 2 shows the call of the RAND subroutine. The disassembled mnemonics on line 6 shows the first instruction executed in the RAND subroutine. To display more lines of the trace, select: Analysis Display Notice that the starting and ending lines are incremented by the number of lines given in the last display command.
  • Page 50 In the display above, you see remaining execution of the instructions in the RAND subroutine. To display more lines in the trace, press CTRL-R to repeat the previous command. Since you pressed Enter in the previous command to select the automatically incremented starting and ending line numbers, the automatically incremented line numbers are selected again, and the next 16 lines of the trace are displayed.

  • Page 51: Using Storage Qualifiers

    In the trace list above you see the instructions that write the random number to the RESULTS area. Using Storage In the last example, all captured states were stored. To modify the trace specification of the previous example so that only the states Qualifiers which write random numbers to the RESULTS area are stored, select: Analysis, Trace, Modify...

  • Page 52: Figure 3-5. Storage Qualifier Specification

    Figure 3-5. Storage Qualifier Specification 3-16 Examples...
  • Page 53 After the "Trace complete" message is shown on the status line, display the trace by selecting: Analysis, Display Type the number of the starting state plus 15 into the ending state field, and press Enter. The resulting trace will be similar to the display shown below.

  • Page 54: Using Trace Prestore

    Using Trace Prestore lets you to save up to two states which precede a normal store state. The following example uses a prestore qualifier to show which Prestore caller of WRITE_NUMBER corresponds to each value written to the RESULTS area. Because you know the BSR assembly language instruction is used to call a subroutine, you can qualify prestore states as states whose data equals the BSR opcode (6100H).
  • Page 55 Figure 3-6. Prestore Qualifier Specification (Cont’d) To begin the trace, select: Analysis, Begin After the "Trace complete" message is shown on the status line, display the trace by selecting: Analysis, Display Type the number of the starting state plus 15 into the ending state field, and press Enter.
  • Page 56 The prestore state immediately preceding each write state shows the address of the caller. The analyzer uses the same resource to save prestore states as it does to save count tags. Consequently, the "prestore" string is shown in the "count" column of the trace list. Note that the time counts are relative to the previous normal storage state.

  • Page 57: Changing The Count Qualifier

    Changing the Suppose now that you are interested in only one address in the RESULTS area, say 5C2H. You wish to see how many loops of the Count Qualifier program occur between each write of a random number to this address. You can set up the trace specification so that only writes to address 5C2H are stored;...
  • Page 58 Figure 3-7. Count Qualifier Specification (Cont’d) To begin the trace, select: Analysis, Begin After the "Trace complete" message is shown on the status line, display the trace by selecting: Analysis, Display Type the number of the starting state plus 15 into the ending state field, and press Enter.
  • Page 59 The trace listing above shows that the program executes a variable number of times for each time that a random number is written to 5C2H. Where counts of 0 are seen, the sample program is executing in the QSORT routine which sorts the values written to the RESULTS area.

  • Page 60: Using "Restart On" Branches

    Using "Restart Selecting "restart on" branches is useful in some situations to trace a specific combination of events. For example, CALLER_3 can be used On" Branches to write any random number, but suppose you want to trace only the situation where CALLER_3 is used to write a random number to address 5C2H.

  • Page 61: Figure 3-8. Branches "Restart On" Specification

    Figure 3-8. Branches "Restart On" Specification Examples 3-25...
  • Page 62 To begin the trace, select: Analysis, Begin After the "Trace complete" message is shown on the status line, display the trace by selecting: Analysis, Display Type -7 into the starting state field and 8 into the ending state field, and press Enter.

  • Page 63: Using Branches "Per Level

    Using Branches Selecting branches "per level" in the trace specification gives you access to the full power and flexibility of the analyzer. Branches per "Per Level" level are used when you need to trace more complicated conditions. There is a "bug" in this chapter’s sample program. Occasionally, after the 256 bytes of the RESULTS area have been sorted by the QSORT subroutine, you will see a byte out of order in the last eight or so bytes of the area.
  • Page 64 pgpbssAGAIN and press Enter. Continue typing: pgpmdbRESULTS..RESULTS+0ffh and press Enter. Terminate the kestroke macro by pressing ESC. Before executing the F3 keystroke macro, define breakpoints at QSORT and AGAIN by selecting: Breakpoints, Add Type in "QSORT;AGAIN" into the breakpoint addresses field, and press Enter.

  • Page 65: Figure 3-9. Tracing Last Write To Results Area

    display again. Sometimes, the program seems to work correctly; other times, you will see a byte out of order. The memory display shows that the QSORT routine works for the most part, which makes it look like the problem occurs on the final write to the RESULTS area.
  • Page 66 Figure 3-9. Tracing Last Write to RESULTS (Cont’d) To begin the trace, select: Processor, Go, Pc Analysis, Begin After the "Trace complete" message is shown on the status line, display the trace by selecting the following commands: Window, Zoom Use the Tab key to select the "Analysis" window, and press Enter. Now to display the trace, select: Analysis, Display Enter the first state to display in the starting state field, and the starting...
  • Page 67 From the previous trace, you see that the final writes made in the QSORT subroutine are indeed improper values for that part of the RESULTS area. Displaying additional lines of the trace shows you that it is common for bad values to be written to 5FEH. You can set up a trace to trigger on one of the bad writes to 5FEH, and store all the states which lead up to this event.
  • Page 68 2. If a write of an inappropriate value (80H through 0FFH) to address 5FEH occurs, this may or may not be the trigger event -- another condition must be tested (see 3). Else, if the QSORT routine exits before a write of a bad value to 5FEH occurs, the trigger event has not occurred in this loop of the program;...

  • Page 69: Figure 3-10. Branches "Per Level" Specification

    Figure 3-10. Branches "Per Level" Specification Examples 3-33...
  • Page 70 To begin the trace, select: Analysis, Begin After the "Trace complete" message is shown on the status line, display the trace by selecting: Analysis, Display Display all the lines in the trace. After the trace is displayed, use the PgUp to find the sequence branch prior to the trigger. From the trace display above, you can see that the instructions at addresses 4CAH and 4CEH are the ones that cause the problems.
  • Page 71 INC_LOW loop. Changing the program in the following manner will fix the problem (notice the instructions surrounded by the "#" character). ************************************************** * The QSORT subroutine is passed (on the stack) * the high and low addresses of an area of bytes * to be sorted.

  • Page 72: Storing "Windows" Of Program Execution

    ;------------------------------------------------- ; If high index is greater than low index, swap ; values and move indexes again. ;------------------------------------------------- MOVE.B [A0],D3 MOVE.B [A1],[A0] MOVE.B D3,[A1] BRA.B INC_LOW ;------------------------------------------------- ; A0 = low address (needed to swap dividing value). ;------------------------------------------------- MOVE.L 4[A7],A0) ;------------------------------------------------- ;...

  • Page 73: Figure 3-11. Storing A Window Of Program Execution

    found, the analyzer proceeds to the second sequence level which stores the states you’re interested in while searching for the window disable state. If you want to store the window before and after the trigger, use two sets of paired sequence levels: one window enable/disable pair of sequence terms before the trigger, and the another disable/enable pair after the trigger (see figure 3-11).

  • Page 74: Figure 3-12. Store "Window" Trace Specification

    To set up this trace specification, select: Analysis, Trace, Modify Modify the trace specification as shown in figure 3-12. Figure 3-12. Store "Window" Trace Specification 3-38 Examples...
  • Page 75 Figure 3-12. Store "Window" Trace Spec. (Cont’d) To begin the trace, select: Analysis, Begin After the "Trace complete" message is shown on the status line, display the trace by selecting: Analysis, Display Enter -8 in the starting state field and 7 in the ending state field to display the following lines of the trace.
  • Page 76 Display more lines of the trace by selecting: Analysis, Display Press the Enter key twice to select the automatically incremented starting state and ending state numbers to display the following lines of the trace. 3-40 Examples...
  • Page 77 Excluding Windows You can use the sequencer to exclude windows of program execution by switching the storage qualifiers on the enable and disable sequence of Program Execution levels (see figure 3-13). In other words, store the states you’re interested in while searching for the enable state and do not store states while searching for the disable state.

  • Page 78: Excluding Windows Of Program Execution

    Figure 3-13. Excluding Windows of Program Execution Triggering on a State In the previous example, the trigger state occurred inside the window, between two sequence levels that searched for the window enable state. Outside the Window You can set up a trace specification that triggers on a state outside the window by having the trigger occur between two sequence levels that search for the window enable state as shown in figure 3-14.

  • Page 79: Figure 3-14. Triggering On A State Outside The Window

    Figure 3-14. Triggering on a State Outside the Window Examples 3-43...

  • Page 80: Using Multiple Trigger Levels

    Using Multiple It is possible for the analyzer to trigger when finding a state in any sequence level but the last because the trigger point is not actually Trigger Levels when the analyzer finds the state specified in the "Trigger on" field;...
  • Page 81 The "Trace complete" message is shown on the status line, indicating that the analyzer has indeed triggered. Examples 3-45...
  • Page 82 Notes 3-46 Examples...

  • Page 83: Using The External Analyzer

    Using the External Analyzer Introduction Most HP 64700 Series emulators may be ordered with an external analyzer. The external analyzer provides 16 external data channels. These data channels allow you to capture activity on signals external to the emulator, typically other target system signals. The external...

  • Page 84: Before You Can Use The External Analyzer

    Before You Can There are several things to do before you can use the external analyzer; these things are listed below and explained in the following paragraphs. Use the External Analyzer Assemble the analyzer probe. Connect the probe to the emulator. Connect the probe wires to the target system.

  • Page 85: Figure 4-1. Assembling The Analyzer Probe

    Figure 4-1. Assembling the Analyzer Probe Each of the 18 probe wires has a signal and a ground connection. Each probe wire is labeled for easy identification. Thirty-six grabbers are provided for the signal and ground connections of each of the 18 probe wires.

  • Page 86: Connecting The Probe To The Emulator

    Figure 4-2. Attaching Grabbers to Probe Wires Connecting the The external analyzer probe is attached to a connector under the snap-on cover in the front upper right corner of the emulator. Remove Probe to the Emulator the snap-on cover by pressing the side tabs toward the center of the cover;...

  • Page 87: Figure 4-3. Removing Cover To Emulator Connector

    Figure 4-3. Removing Cover to Emulator Connector Each end of the ribbon cable connector is keyed so that it can be connected to the emulator in only one way. Align the key of the ribbon cable connector with the slot in the emulator connector, and gently press the ribbon cable connector into the emulator connector.

  • Page 88: Figure 4-4. Connecting The Probe To The Emulator

    Figure 4-4. Connecting the Probe to the Emulator 4-6 Using the External Analyzer...

  • Page 89: Connecting Probe Wires To The Target System

    Caution Turn OFF target system power before connecting analyzer probe wires to the target system. The probe grabbers are difficult to handle with precision, and it is extremely easy to short the pins of a chip (or other connectors which are close together) with the probe wire while trying to connect it.

  • Page 90: Figure 4-5. Connecting The Probe To The Target System

    Figure 4-5. Connecting the Probe to the Target System 4-8 Using the External Analyzer...

  • Page 91: Specifying Threshold Voltages & Defining Labels

    Specifying Threshold To specify threshold voltages for the external probe signals, select: Voltages & Defining Labels Analysis, Format, Internal An example format specification display is shown in figure 4-6. This screen allows you to specify threshold voltages, informs you of activity on the external analyzer trace signals, and allows you to define external analyzer labels.

  • Page 92: Specifying Threshold Voltages

    Specifying Threshold Voltages The external probe signals are divided into two groups, the lower byte (channels 0 through 7), and the upper byte (channels 8 through 15). Threshold voltage levels can be specified for each group. When the cursor is in one of the threshold voltage fields, you can use the Tab key to select one of the following values, or you can type in the voltage: 1.4 volts.

  • Page 93: Selecting The External Analyzer Mode

    The independent state analyzer is identical to the emulation analyzer, except that only 16 bits of analysis are available. Your HP 64700 Series emulator now contains two state analyzers; two sets of analyzer resources (trace memory, patterns, qualifiers, etc.) are available, one for the emulation analyzer and one for the independent state analyzer.

  • Page 94: Using The External Analyzer When Aligned With Internal

    (Refer to the "Making Coordinated Measurements" chapter for more information on cross-triggering.) external timing In this mode, the external analyzer operates as an analyzer independent timing analyzer. Refer to the "Using the External Timing Analyzer" for more information. Using the External When the "aligned with internal"...

  • Page 95: Figure 4-7. External Data In The Trace

    Figure 4-7. External Data in the Trace Using the External Analyzer 4-13...

  • Page 96: Using The External State Analyzer

    Using the External When you select the "external state analyzer" mode, the external analyzer operates as an independent state analyzer. You use the State Analyzer independent state analyzer in the same way as you use the internal analyzer, except that you must select the external analyzer clock source and specify the maximum qualified clock speed.

  • Page 97: Figure 4-9. Qualified Clocks

    fields and press the Tab key repeatedly to view the following selections. <rising edge> Selects the rising edge of this signal as the clock. <falling edge> Selects the falling edge of this signal as the clock. <both edges> Specifies that the external analyzer be clocked on both the rising and falling edges of this signal.

  • Page 98: Specifying The Maximum Qualified Clock Speed

    the qualifying signal is lower than the threshold voltage. Specifies that this signal is not used. When edges are specified for both the J and K signals, the external analyzer clocks on any of the specified edges. Setup time for qualifying signals is approximately 20 nanoseconds. Qualifying signal hold time is approximately 5 nanoseconds.

  • Page 99: External Analyzer Specifications

    External Analyzer Specifications Threshold Accuracy = +/- 50 mV. Threshold Voltage Range = 6 V to -6 V. Dynamic Range = +/- 10 V about threshold setting. Minimum Input Swing = 600 mV pp. Minimum Input Overdrive = 250 mV or 30% of threshold setting, whichever is greater.
  • Page 100 Minimum Clock Period: – No Tagging Mode = 40 ns (25 Mhz clock). – Event Tagging Mode = 50 ns (20 MHz clock). – Time Tagging Mode = 60 ns (16 MHz clock). Minimum Time from Slave Clock to Master Clock = 10 ns. Minimum Time from Master Clock to Slave Clock = 50 ns.

  • Page 101: Using The External Timing Analyzer

    Using the External Timing Analyzer Introduction The external analyzer can be aligned with the internal emulation analyzer, configured as an external state analyzer, or configured as an external timing analyzer. This chapter shows you how to use the external timing analyzer. The main sections in this chapter: Show you how to configure the external analyzer as a timing analyzer.

  • Page 102: Prerequisites

    Prerequisites Before you can use the external timing analyzer, you must have already completed the following tasks: You must be using the version of the PC Interface that gives you access to the external timing analyzer. The external analyzer probe must be assembled and connected to signals of interest as shown in the "Using the External Analyzer"...

  • Page 103: Specifying Threshold Voltages & Defining Labels

    Trigger position Trigger delay Duration Figure 5-1. Timing Interface Main Display Specifying To specify threshold voltages for the external probe signals, select: Threshold Voltages & Defining Labels Analysis, Format, External An example format specification display is shown in figure 5-2. This screen allows you to specify threshold voltages, informs you of activity on the external analyzer trace signals, and allows you to define timing labels.

  • Page 104: Threshold Voltages

    Figure 5-2. Timing Label Specification When you are done specifying the threshold voltages and defining labels, press End and Enter to save your specifications. To exit without making changes to this label configuration, press Esc. Threshold Voltages The external probe signals are divided into two groups, the lower byte (channels 0 through 7), and the upper byte (channels 8 through 15).

  • Page 105: Activity

    <number> You can type in a threshold voltage. Voltages may be from -6.4 volts to 6.35 volts with a 50 mV resolution. Activity This line of the display shows the activity on the external trace signals. A trace signal is specified as low (0) when it is below the threshold voltage, high (1) when it is above the threshold voltage, or moving (double headed arrows).
  • Page 106 Analysis, Trace, Modify, External Brackets, [ ], in the timing specification display indicate fields in which the Tab key may be used to select choices. When you are done modifying the timing specification, press End and Enter to save your specifications. To exit without making changes to the timing specification, press Esc.

  • Page 107: Acquisition Modes

    Figure 5-3. Transitional Acquisition Mode Acquisition Modes You can use the external timing analyzer in one of three modes: transitional, standard (data acquisition), or glitch (data and glitch acquisition). Transitional In the transitional mode, data is sampled at 100 MHz, but stored only when an input transition (on any channel) is detected.

  • Page 108: Figure 5-4. Standard Acquisition Mode

    Figure 5-4. Standard Acquisition Mode Figure 5-5. Glitch Acquisition Mode 5-8 Using the External Timing Analyzer...

  • Page 109: Standard

    Standard In the standard mode, the timing analyzer samples data on the external analyzer probe at the selected sample rate. Up to 1024 samples can be stored, and the maximum sample rate is 100 MHz (10 ns intervals). See figure 5-4. Glitch This is the same as the standard acquisition mode except that glitch information is also stored at each sample.

  • Page 110: Trig1 Or Trig2

    TRIG1 or TRIG2 When "Armed by TRIG1" or "Armed by TRIG2" is shown, the external analyzer cannot perform a measurement until the arm is received from an external trigger signal. External trigger signals can drive the external analyzer over the TRIG1 or TRIG2 signals, as specified in the Trigger Configuration (see the "Allowing CMB and BNC Triggers to Arm the Analyzer"...

  • Page 111: Label Qualifier

    Label Qualifier The "Label" field in the timing specification display allows you to select one of the defined labels. You can use the Tab key to scroll through the defined labels. Once a label is selected, you can then specify patterns, edges, or glitches on the data channels associated with that label.

  • Page 112: Find Pattern

    These three types of trigger conditions are described below. Find Pattern Find pattern allows you to specify a data pattern consisting of 1’s, 0’s, or X’s (don’t cares) across the 16 channels. The most significant bit is channel 15 and least significant bit is channel 0. Use the field editing keys to position the cursor to the different channels, and use the Tab key to select the appropriate value.

  • Page 113: Figure 5-6. Pattern Trigger

    Figure 5-6. Pattern Trigger Using the External Timing Analyzer 5-13...

  • Page 114: Then Find Edge Or Glitch

    Then Find Edge or Edge or glitch triggers occur after the pattern has been present on the probe for the specified duration and, while the pattern is still present, Glitch an edge or glitch occurs on any of the selected channels. Edges on each channel can be specified as rising, falling, or either rising or falling.

  • Page 115: Figure 5-7. Edge Trigger

    Figure 5-7. Edge Trigger Using the External Timing Analyzer 5-15...

  • Page 116: Figure 5-8. Glitch Trigger

    Figure 5-8. Glitch Trigger 5-16 Using the External Timing Analyzer...

  • Page 117: Timing Waveform Display

    Timing Waveform To view a timing waveform display, select: Display Analysis, Display, External You can exit the waveform display by pressing ESC, and you can re-enter the waveform display by selecting the "Analysis Display External" command. When you enter the waveform display, there are several fields which allow you to change how the trace information is displayed.

  • Page 118: Scrolling Through The Waveform Display

    Scrolling through the When the time per division is decreased, not all of the trace can be displayed on the screen. However, you can scroll the trace across the Waveform Display screen by pressing the CTRL left arrow and CTRL right arrow keys. The portion of the trace that is currently displayed is represented by a bar at the bottom of the screen.

  • Page 119: Inserting/Deleting Channels

    Inserting/Deleting The Insert key allows you to increase the number of channels included in the waveform display. By inserting channels, you can display a Channels maximum of 16 channels on the display. Each channel can be used to display any of the defined labels. The Delete key allows you to decrease the number of waveforms included on the display.

  • Page 120: External Timing Analyzer Specifications

    External Timing Sample Rate Accuracy = 0.01% Analyzer Specifications Asynchronous Pattern. Trigger on pattern less than or greater than specified duration. Pattern is logical AND of specified low, high, or "don’t care" for each channel. If pattern is true then false for less than the duration, there is a 20 ns reset time before looking for the pattern again.

  • Page 121: Making Coordinated Measurements

    Coordinated measurements are measurements synchronously made in multiple emulators or analyzers. Coordinated measurements can be made between HP 64700 Series emulators which communicate over the Coordinated Measurement Bus (CMB). Coordinated measurements can also be made between an emulator and some other instrument connected to the BNC connector.
  • Page 122 Note You must use the background emulation monitor to perform coordinated measurements. Refer to your PC Interface: Emulator User’s Guide for more information on the emulation monitor. Three signal lines on the CMB are active and serve the following functions when enabled: TRIGGER Active low.

  • Page 123: Tracing At Execute

    Tracing at To specify that an analyzer measurement begin upon reception of the CMB EXECUTE signal, select the following PC Interface command: EXECUTE Analysis, CMB, Begin The trace measurement defined by the current trace specification will be started when the EXECUTE signal becomes active. When the trace measurement begins, you will see the message "ALERT: CMB execute;...

  • Page 124: Using The Analyzer Trigger To Drive External Signals

    Figure 6-1. Cross Trigger Configuration Both the emulation analyzer and the external analyzer may drive the same internal signal; in this case, the internal signal will be driven by the analyzer that finds its trigger condition (point) first. Using the To specify that external TRIGGER signals (either CMB or BNC) become active when the analyzer trigger condition is found, access the Analyzer Trigger...

  • Page 125: Allowing Cmb Or Bnc Triggers To Arm The Analyzer

    select the single-headed arrow pointing towards TRIG2; this shows that the analyzer trigger is driving TRIG2. Next, highlight the "CMB" field and use the Tab key to select the single-headed arrow pointing towards CMB; this shows that the CMB TRIGGER signal becomes active when the TRIG2 signal is driven. This trigger configuration is also shown in figure 6-1.

  • Page 126: Arming The External Analyzer

    Figure 6-2. Receiving External Signals In the internal emulation analyzer trace specification display, you can use the "arm" resource in any of the state qualifier fields. For example, if "arm" is shown in the "trigger on" field, the analyzer triggers when it is armed.

  • Page 127: Using One Analyzer To Arm The Other

    This trigger configuration is shown in figure 6-2. In the external state analyzer trace specification display, you can use the "arm" resource in any of the state qualifier fields. For example, if "arm" is shown in the "trigger on" field, the analyzer triggers when it is armed.

  • Page 128: Other Trigger Combinations

    Figure 6-3. Using One Analyzer to Arm the Other Other Trigger You may have noticed that the CMB or BNC TRIGGER signals may be driven by the internal TRIG1 and TRIG2 signals, be received by Combinations external sources, or both. When a CMB or BNC signal is received from an external source, it may be used to break emulator execution into the monitor.
  • Page 129 When an emulator break occurs due to the analyzer trigger, the analyzer will stop driving the internal signal that caused the break. Therefore, if TRIG2 is used both to break and to drive the CMB TRIGGER (for example), TRIGGER will go true when the trigger is found and then will go false after the emulator breaks.
  • Page 130 Notes 6-10 Making Coordinated Measurements...
  • Page 131 Index absolute count display, 2-16 absolute files, loading, 3-9 acquisition modes, 5-7 activity, external trace channels, 4-10, 5-5 add operator, 2-9 addr trace label, 2-10 analysis begin, 2-13 analysis display, 2-14 analysis halt, 2-14 analysis specification trace at EXECUTE, 6-3 analyzer features of, 1-3 internal, using the, 2-1...
  • Page 132 CMB (coordinated measurement bus), 6-1 signals on, 6-2 CMOS threshold voltage specification, 4-10, 5-4 constants, 2-8 coordinated measurements, 1-5 definition, 6-1 count information in the trace listing, 1-3 count information in trace listing, 2-15 count qualifiers, 2-6, 3-21 counts displaying relative or absolute, 2-16 cross-arming emulation and external analyzers, 6-7 data trace label, 2-11 decimal numbers, 2-8...
  • Page 133 external analyzer (cont’d) timing analyzer, using the, 5-1 trace labels, creating, 4-10 using, 4-1 external timing analyzer, 1-4 features of the analyzer, 1-3 find state, 1-3, 2-4 glitch acquisition mode, 5-9 glitch trigger, 5-12, 5-14 global restart state, 2-5 grabbers connecting to analyzer probe, 4-3 greater than duration, 5-12 halting the trace, 2-14...
  • Page 134 modulo operator, 2-9 multiply operator, 2-9 notes Internal and External command options, 2-1 monitors/adapters to display timing waveforms, 1-4 threshold settings take effect when you begin the trace, 4-10 timing interface software, 1-4, 5-1 number bases, 2-8 occurrence counts, 2-5 octal numbers, 2-8 operators, 2-9 interset, 2-12...
  • Page 135 relative display of count information, 2-15 reset emulation analyzer specification, 2-13 timing specification, 5-14 restart on, 3-24 restart state, 2-5 rotate left operator, 2-9 rotate right operator, 2-9 running programs, 3-10 sample period, 5-9 sequence levels, 1-3, 2-2/2-3 deleting, 2-3 inserting, 2-3 maximum, 2-3 setting the trigger level, 2-3...
  • Page 136 timing waveform display, 5-17 trace at EXECUTE, 6-3 definition of, 1-1 description of listing, 2-15 displaying the, 2-14 halting the, 2-14 starting the, 2-13 window, 3-10 trace format, 2-16 trace labels, 2-10 external analyzer, creating, 4-10 timing analyzer, creating, 5-5 trace specification, 2-10 trace specification count qualifier, 3-21...
  • Page 137 TRIGGER, CMB signal, 6-2 TTL threshold voltage specification, 4-10, 5-4 unary one’s complement operator, 2-9 unary two’s complement operator, 2-9 user defined reference points, 5-18 using the external timing analyzer, 5-1 values assigning to pattern and range resources, 2-7 values, predefined for emulator status, 2-11 voltages, threshold, 4-10, 5-4 waveform (timing) display, 5-17 window zoom, 3-10...
  • Page 138 Notes 8-Index...

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