Machxo3 Clock Sources; Figure 4.1. Optional Clock Circuit Design; Table 4.1. Jtag Connections - Lattice Semiconductor MachXO3-940 User Manual

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MachXO3 Clock Sources

The MachXO3-9400 Development Board has four options for the MachXO3 clock sources:
12 MHz from U1
8 MHz from U7
User defined frequency by installing an oscillator in the Y2 (DNI) footprint
Off board clock source from J10 (DNI)
The 8 MHz clock from U7 is the default clock source when building a Platform Manager design. Note that JP1 should be
installed to power the ASC device.
The 12 MHz clock from the FT2232H FTDI device is another clock source. Its use requires JP11 to be installed to connect
the 12 MHz clock signal to the MachXO3 device I/O. JP9 should not be installed to enable U1.

Table 4.1. JTAG Connections

Clock
Signal
Frequency
Name
8 MHz
ASC_CLK
12 MHz
12MHz
User defined
OSC_IN
User defined
OSC_IN
Additional information on using optional clock sources:
The board provides for an optional clock input for the MachXO3 from either the Oscillator (Y2) or the SMA header
(J10) as shown in
Figure
Y2 should be installed by the end user and it should be a 2.5 mm x 2.0 mm 4-SMD package. This is compatible with
the ASDMB serial of the Ultra Miniature Pure Silicon™ Clock Oscillator from Abracon LLC. JP4 can be used to
disable Y2 output by pulling down OSC_EN, which can also be controlled by the L20 pin of MachXO3.
J10 should be installed by the end user. A Complementary Metal-Oxide Semiconductor (CMOS) compatible clock
can then be connected with an SMA cable.
VCCIO1
C97
0.1uF
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0
MachXO3
Clock
Ball
Source
Location
L1
U7
JP1 installed, test point TP14
B10
U1
JP11 installed, JP9 removed
D22
Y2 (DNI)
JP4 removed and OSC_EN signal (MachXO3 ball L20) Logic 1.
Y2 not installed, or OSC_EN signal (MachXO3 ball L20) Logic 0, or JP4
D22
J10 (DNI)
installed.
4.1. Neither of them are populated.
R145 10K
OSC_EN
Y 2
4
1
VDD
Standby
2
3
GND
OUT
ASDMB-XX.XXXMHz
DNI

Figure 4.1. Optional Clock Circuit Design

Comments
JP4
2
1
JUMPER
OSC_IN
OSC_IN
R144
0
EXT_CLK
J10
SMA
DNI
MachXO3-9400 Development Board
Evaluation Board User Guide
[4]
13

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