Summary of Contents for Lattice Semiconductor ECP5-5G
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ECP5-5G™ Versa Development Board User Guide EB103 Version 1.2, January 2016...
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The ECP5-5G Versa Development Board is part of the ECP5-5G Versa Development Kit. The guide is intended to be referenced in conjunction with demo user guides to demonstrate the ECP5-5G FPGA.
Note: The connections referenced in this document refer to the LFE5UM5G-45F-8BG381C device. Applying Power to the Board The ECP5-5G Versa Development Board is ready to power on. The board can be supplied with power from a PCI Express host system or standalone with an external wall power module.
The built-in module consists of a USB Type-B connector and a USB UART device. To use the built-in download cable, simply connect a standard USB cable (a USB-B to USB-A cable is included with the ECP5-5G Versa Devel- opment Kit) from J2 to your PC (with Diamond programming software installed). The USB hub on the PC will detect the addition of the USB function, making the built-in cable available for use with the Diamond programming soft- ware.
Diamond Programmer software connected to the Development board via a standard mini-USB cable. Refer to the ECP5-5G Versa Development Kit Quick Start Guide (QS039) for more details. Once the programming software is installed and the USB cable is connected to the board, the programmable devices can be programmed.
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Figure 6. ECP5-5G Status LEDs and Push-button Controls The LEDs indicate the configuration status of the ECP5-5G FPGA. • D17 (red) illuminated indicates that programming was aborted or reinitialized, driving the INITN output low. • D20 (green) illuminated indicates the successful completion of configuration by releasing the open collector DONE output pin.
A Micron N25Q128A device is populated on-board. The Serial SPI Flash memory device can be configured easily via the ECP5-5G JTAG port. This mode enables the FPGA to be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.
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7. From the main programming window, select Program from the top toolbar. This begins the SPI Serial Flash programming. Note that the SPI Flash Background Programming operation is only possible when the ECP5-5G device is either erased or the active design has the MASTER_SPI_PORT mode enabled. For more details see...
(See Appendix A, Sheet 9, Figure 21 - Reference Clock Generator) The ECP5-5G Versa Development Board allows for several clock source options. Some of these options are con- trolled via the ispClock5406D programmable clock manager device. The ispClock5406D enables the reference clock from the PCI Express interface to provide a reference clock to the SERDES.
The PCI Express add-in card specification requires add-in boards to include capabilities to tell the host of its pres- ence. The ECP5-5G Versa Development Board allows this optional connection via a board jumper. Using the board with a PCI Express host requires the setting shown in Figure 10 below.
Figure 12 shows the switches. Note the silk marking associated with SW3-7 is incorrect in revision B, SW3-7 is mapped to K19, per Table 7. Figure 11. ECP5-5G Versa Development Board LEDs and Switches The designated pins are connected according to Table 7.
(See Appendix A, Sheet 8, Figure 20 - LEDs and Switches) The LEDs provided on the ECP5-5G Versa Development Board are connected to general purpose FPGA I/Os. These LEDs provide status for user designs and must be included in the design. The LEDs illuminate when the FPGA output is driven LOW.
DDR3 Memory Device (See Appendix A, Sheet 7, Figure 19 - DDR3 Memory) • The ECP5-5G Versa Development Board is equipped with an SDRAM memory device (1.5 V, 64 Mb/x16, 96-ball FBGA, 933 MHz, DDR3-1866) such as the Micron MT41K64M16TW-107:J device.
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ECP5-5G Versa Development Board Table 10. DDR3 Memory Controller Interconnections FPGA Ball FPGA Ball DDR3 Signal Number DDR3 Signal Number DQ10 DQ11 DQ12 DQ13 DQ14 K_0# DQ15 CAS# DQS0 DQS0# DQS1 DQS1# CS0# RAS# CLKP VREF CLKN RST#...
Table 11. PHY Status Indicators Status Description RJ45 (Yellow) Data RX/TX RJ45 (Green/Orange) Link State Each Marvell 88E1512 device communicates via a RGMII interface to the ECP5-5G device. Table 12. FPGA GPIO to RGMII Interfaces Signal Phy1 Phy2 CLK125 CLK125Pll...
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ECP5-5G Versa Development Board Table 13. Expansion Connections X3 Expansion Connector X4 Expansion Connector FPGA Ball FPGA Ball Signal Number Signal Number — RESOUT# — — — IO29 IO30 IO31 IO32 IO33 IO34 IO35 IO36 IO37 IO38 IO10 IO39 IO11...
ECP5-5G Versa Development Board Appendix B. Bill of Materials Table 14. ECP5-5G Versa Development Board Bill of Materials Item Quantity Reference Part Manufacturer Part Number Description PCI Express x1 Edge Finger Conn. C1,C2,C3,C4,C5,C20,C21, 10NF-0402SMT Panasonic ECJ0EB1E103K CAP .01 uF 25 V...
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ECP5-5G Versa Development Board Item Quantity Reference Part Manufacturer Part Number Description C182,C184,C187,C190, 10NF-0603SMT Kemet C0603C103K5RACTU CAP .01 uF 50 V C192,C194,C196,C198, CERAMIC X7R 0603 C200,C204,C217,C219, C221,C223,C226,C228, C234,C236,C241 C229 6.8UF-TAN-0805SMT Kemet T494R685K006AS CAP TANT 6.8 uF 6.3 V 10% SMD...
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ECP5-5G Versa Development Board Item Quantity Reference Part Manufacturer Part Number Description EXB2HV221JV Panasonic EXB2HV221JV RES ARRAY 220 Ohm 5% 8 RES SMD EXB2HV472JV Panasonic EXB2HV472JV RES ARRAY 4.7K Ohm 5% 8 RES SMD CTS-RT1402B7 CTS Corporation Resis- RT2402B7 RES NET DDR SDRAM...
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ECP5-5G Versa Development Board Item Quantity Reference Part Manufacturer Part Number Description R63,R64,R66,R67,R70 Vishay Dale WSL2010R1000FEA RES .1 Ohm 1/2 W 1% 2010 SMD R71,R75 2_2K-0603SMT-DNI R73,R74,R107,R108,R156 100R-0402SMT Panasonic ERJ-2RKF1000X RES 100 Ohm 1/10 W 1% 0402 SMD 0R-0603SMT-DNI R85,R99,R111,R114...
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ECP5-5G Versa Development Board Item Quantity Reference Part Manufacturer Part Number Description LP2998-SO8 National LP2998MAX/NOPB Termination regulator ispCLOCK5406D LATTICE SUPPLIED ISPPAC-CLK5406D- 01SN48I U14,U15 88E1512_56QFN Marvell 88E1512-A0-NNP2C000 SINGLE-PORT EEE GIGABIT ETHER U44,U45 R0_1-3 Panasonic ERJ-3GEY0R00V RES 0.0 Ohm 1/10 W 0603 SMD...
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