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MachXO3-9400 Development Board
Evaluation Board User Guide
ASC Connections
8.1. ASC Interface
The MachXO3-9400 Development Board provides the dedicated ASC Interface (ASC-I/F) between the onboard ASC
device and the MachXO3 Bank 4. The Platform Manager design in the MachXO3 monitors signal status and controls
output behavior of the ASC through the ASC-I/F. The ASC I
microcontroller for ASC background programming, interface configuration, and additional data transfer such as
parameter measurement or I/O status control.
Table 8.1. ASC to MachXO3 Connections
MachXO3 Ball
ASC Connections
I2C_SDA0
I2C_SCL0
ASC_ CLK
ASC_RESETb
ASC_WRCLK
ASC_RDAT
ASC_WDAT
I2C_WRITE_PROTECT
8.2. ASC Voltage Monitor
ASC Voltage Monitors (VMONs) are connected to various power sources on the board as listed in
Table 8.2. ASC VMON Connections
Power Name
+1.2V**
GND*
VCC1_8FT**
GND*
+3.3V_RASP**
GND*
+3.3V_AR**
GND*
VBUS_5V**
-
POT***
-
+3.3V_ASC**
Notes:
* Connection to GND is through 100 Ω (R109 – R112) so that the test point can overdrive.
** Connection to the supply is through 270 Ω (R1104 – R108, R182) so that the test point can overdrive.
*** Connection to POT is through 1 kΩ (R277) so that the test point can overdrive.
A 10 kΩ POT is used to provide voltage variation from 0 V - 3.3 V to ASC VMON7 as shown in
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30
ASC Pins
Location
A12 (K2)
14
B12 (K1)
15
L1
7
L3
43
M1
6
N1
5
P1
4
N2
44
ASC Signal Name
ASC_VMON1
ASC_GS_VMON1
ASC_VMON2
ASC_GS_VMON2
ASC_VMON3
ASC_GS_VMON3
ASC_VMON4
ASC_GS_VMON4
ASC_VMON5
ASC_VMON6
ASC_VMON7
ASC_VMON8
ASC_VMON9
2
C interface is used by the FPGA or an external
Description
2
I
C data programming (user control)
I
2
C clock programming (user control)
8 MHz clock output from ASC
ASC device reset (Active Low)
ASC-I/F clock signal to ASC
ASC-I/F data signal from ASC
ASC-I/F data signal to ASC
2
I
C Configuration Write Control signal when
WP[1:0] = 10 in ASC WRITEPROTECT_USERTAG
Register, pull high to enable overwriting by I
instructions.
ASC Pin Number
26
25
28
27
30
29
32
31
34
35
36
37
38
ASC Breakout
Test Point
TP2
TP1
TP14
TP13
TP12
TP11
TP10
Share with
TP44 for
2
C
ASC_LED1 if
R99 is DI
Table
8.2.
ASC Breakout Test Point
TP15
TP16
TP17
TP19
TP18
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
Figure
8.1.
FPGA-EB-02004-1.0
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