Fx12 Headers (Dni); Table 5.7. Fx12 U4 Header Pin Connections - Lattice Semiconductor MachXO3-940 User Manual

MachXO3-9400 Development Board
Evaluation Board User Guide

5.3. FX12 Headers (DNI)

The board provides two headers – U4 and U5 to connect to FX12 compatible boards or cables. Each header has eight
pairs of Low-Voltage Differential Signaling (LVDS) signals for high speed data receiver.

Table 5.7. FX12 U4 Header Pin Connections

U4 Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
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18
Signal Name
CH0_DCK_P
CH0_DCK_N
GND
CH0_DATA0_P
CH0_DATA0_N
GND
CH0_DATA2_P
CH0_DATA2_N
GND
FX_SN*
FX_SCLK*
PWR_12V**
SDA2
SCL2
GND
CH2_DATA0_P
CH2_DATA0_N
GND
CH2_DCK_P
CH2_DCK_N
PWR_12V**
RESETN
PWR_5-0V*
CH0_DATA1_P
CH0_DATA1_N
PWR_3-3V*
CH0_DATA3_P
CH0_DATA3_N
PWR_1-8V*
FX_MOSI*
FX_MISO*
PWR_1-8V*
GND
GND
PWR_3-3V*
CH2_DATA1_P
CH2_DATA1_N
MachXO3 Ball Location
AA10
AB10
—
AA4
AB4
—
AA5
AB5
—
—
—
—
AB13
AA13
—
AA6
AB6
—
AA7
AB7
—
AB3
—
AA2
AB2
—
AA8
AB8
—
—
—
—
—
—
—
AA9
AB9
FPGA-EB-02004-1.0