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MachXO3-9400 Development Board
Evaluation Board User Guide
Note:
The LEDs are not lined up in sequence, as shown in
7.4. LVDS Outputs Pins
The MachXO3-9400 Development Board provides nine pairs of unused LVDS outputs pins that are connected to test
points for possible customer applications. The LVDS test points are detailed in
Table 7.4. LVDS Test Points
Signal Name
LVDS_OUT0_P
LVDS_OUT0_N
LVDS_OUT1_P
LVDS_OUT1_N
LVDS_OUT2_P
LVDS_OUT2_N
LVDS_OUT3_P
LVDS_OUT3_N
LVDS_OUT4_P
LVDS_OUT4_N
LVDS_OUT5_P
LVDS_OUT5_N
LVDS_OUT6_P
LVDS_OUT6_N
LVDS_OUT7_P
LVDS_OUT7_N
LVDS_OUT8_P
LVDS_OUT8_N
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
Figure 7.4. Board LEDs
MachXO3 Ball Location
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B8
A8
B9
A9
B11
A11
Figure
7.4.
Table
7.4.
Test Point
TP63
LVDS output pair 0
TP64
TP65
LVDS output pair 1
TP66
TP67
LVDS output pair 2
TP68
TP69
LVDS output pair 3
TP70
TP71
LVDS output pair 4
TP72
TP73
LVDS output pair 5
TP74
TP75
LVDS output pair 6
TP76
TP77
LVDS output pair 7
TP78
TP79
LVDS output pair 8
TP80
Comments
FPGA-EB-02004-1.0
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