Fpga Clock Management - Lattice Semiconductor LatticeECP2M PCI Express x4 User Manual

Lattice Semiconductor
Configuration Status Indicators
(see Appendix A, Figure 8)
These LEDs indicate the status of configuration to the FPGA.
• D8 (RED) illuminated, this indicates that the programming was aborted or reinitialized driving the INITN output
low.
• D11 (GREEN) is illuminated, this indicates the successful completion of configuration by releasing the open col-
lector DONE output pin.
• D12 (GREEN) will flash indicating TDI activity.
• D10 (RED) illuminated, this indicates that PROGRAMN is low.
• D9 (RED) illuminated, this indicates that GSRN is low.
PROGRAMN and GSRN
(see Appendix A, Figure 8)
These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3) and GSRN (SW2).
Depressing the button drives a logic level "0" to the device.
CFG [2:0]
(see Appendix A, Figure 8)
The FPGA CFG pins are set on the board for a particular programming mode via the SW1 DIP switch. JTAG pro-
gramming is independent of the MODE pins and is always available to the user
On-Board Flash Memory
(see Appendix A, Figure 8)
Two memory devices (U10 and U12) are on-board for non-volatile configuration memory storage. These two
devices occupy the same Flash slot on the board. U10 can be populated with an 8M or smaller 8-pin SOIC device.
U12 can be used in place of U10 with a 16-pin TSSOP 64M Flash device. U15 always supplies as an 8M Flash
device. J11 is used to control the selection of the Flash memory to be accessed.

FPGA Clock Management

(see Appendix A, Figure 12)
The evaluation board includes various features for generating and managing on-board clocks. The clocks are gen-
erated from either input provided from SMAs (see table below) or from crystal oscillators (Y1 and Y2). Y1 is sock-
eted for interchangeability and Y2 is a 100MHz surface-mounted oscillator which is fanned out around U1 for
reference clocks with a fan-out buffer IC.
Y1 can be a 4-pin DIP type oscillator like the Connor-infield XO-400 series.
Both of these input clock sources are routed through the Lattice ispClock5620A devices (U2). These programmable
clock management devices allow for clock synthesis and buffering.
U2 is a Lattice ispClock5620A in-system programmable analog circuit that allows designers to implement clock dis-
tribution networks supporting multiple synchronized output frequencies using a single integrated circuit. By inte-
grating a Phase-Locked Loop (PLL) along with multiple output dividers, the ispClock5620A can derive up to five
SMA Signal
J35 U2 Reference + Input
J36 U2 Reference - Input
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LatticeECP2M PCI Express x4
Evaluation Board User's Guide