General Purpose Ddr Outputs; Table 7.5. Gddr Test Points - Lattice Semiconductor MachXO3-940 User Manual

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7.5. General Purpose DDR Outputs

Graphics Double Data Rate (GDDR) signals are wired to the test pads for signal validation.

Table 7.5. GDDR Test Points

Signal Name
GDDR_DQ0
GDDR_DQ1
GDDR_DQ2
GDDR_DQ3
GDDR_DQ4
GDDR_DQ5
GDDR_DQ6
GDDR_DQ7
GDDR_DQS
GDDR_DQSN
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0
MachXO3 Ball Location
R22
R21
T22
T21
Y22
W21
AA22
Y21
N22
P21
MachXO3-9400 Development Board
Evaluation Board User Guide
Test Point
TP93
TP94
TP95
TP96
TP97
TP98
TP99
TP100
TP101
TP102
29

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