Fpga Clock Management - Lattice Semiconductor LatticeSC PCI Express x1 User Manual

LatticeSC PCI Express x1
Lattice Semiconductor Evaluation Board User's Guide
• D5 (GREEN) is illuminated: This indicates the successful completion of configuration by releasing the open col-
lector DONE output pin.
• D1 (GREEN) will flash indicating TDI activity.
• D4 (RED) illuminated: This indicates that PROGRAMN is low.
• D3 (RED) illuminated: This indicates that GSRN is low.
PROGRAMN and GSRN
(see Appendix A, Figure 5)
These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3) and GSRN (SW2).
Depressing the button drives a logic level "0" to the device.
Bank1 VCCIO
(see Appendix A, Figure 6)
VCCIO1 can be selected on the board to be either 3.3V or 2.5V using J5.
A jumper shunt placed between pin 1 and pin 2 will connect 2.5V. A jumper shunt between pin 2 and pin 3 will con-
nect 3.3V.
On-Board Flash Memory
(see Appendix A, Figure 5)
Two memory devices (U2 and U3) are on-board for non-volatile configuration memory storage. These two devices
occupy the same Flash slot on the board. U2 can be populated with an 8M or smaller 8-pin SOIC device. U3 can be
used in place of U2 with a 16-pin TSSOP 64M Flash device. This is the factory supplied Flash memory configura-
tion. U4 is always supplied as an 8M Flash device. SW1 is used to control the selection of the Flash memory to be
accessed.
Refer to Lattice technical note TN1100, SPI Serial Flash Programming Using ispJTAG™ on LatticeSC FPGAs for
recommended procedures and software usage. To use both SPI Flash devices to program the LatticeSC device,
the user must write to the Flash devices individually. This is accomplished by setting SW1 accordingly. Writing to
Flash #1(U2 OR U3), close 3 and 5 switch positions (ON) and open all others. Writing to Flash #2(U4), close 2 and
4 switch positions (ON) and open all others. For reading from the Flash devices individually, use the same switch
settings as described for writing. For reading from both Flash devices in cascading format, close switch positions
(1, 3, 4, 5, 8).

FPGA Clock Management

(see Appendix A, Figures 10 and 11)
The evaluation board includes various features for generating and managing on-board clocks. The clocks are gen-
erated from either input provided from SMAs (see Table 5) or from crystal oscillators (Y1 and Y4). Y1 and Y4 are
socketed for interchangeability. Y2 and Y5 are 321.25MHz surface-mounted oscillators. The Y3 oscillator is fanned
out around U1 for reference clocks with a fan-out buffer IC.
Y1 and Y4 can be a 4-pin DIP type oscillator like Connor-Winfield XO-400 series.
Clock oscillators are selected per quad. Y1 and Y2 can source a clock to the Left SERDES Quads. Y4 and Y5 can
source a clock to the Right SERDES Quad. The user needs to select the appropriate oscillator by placing jumper
shunts on J20 and/or J22 for the Left reference clock source or J25 and/or J28 for the Right reference clock source.
The selection of these clock sources is dependent on the selection pins of the clock multiplexers. The mux select
pins are driven from the FPGA and will need to be driven according to the needs of the user design. The following
table defines the selection of the clock sources.
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