Lattice Semiconductor MachXO3-940 User Manual page 3

Figures
Figure 1.1. Top View of MachXO3-9400 Development Board .............................................................................................. 6
Figure 1.2. Bottom View of MachXO3-9400 Development Board ........................................................................................ 7
Figure 2.1. Board Power Supply............................................................................................................................................ 9
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Figure 3.1. JTAG/I C Programming Architecture ................................................................................................................ 11
Figure 3.2. PTM Programming Mode ................................................................................................................................. 11
Figure 4.1. Optional Clock Circuit Design ............................................................................................................................ 13
Figure 5.1. Aardvark SS Pin Connections ............................................................................................................................ 20
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Figure 6.1. I C Topology ...................................................................................................................................................... 23
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Figure 6.2. I C MUX Circuits ................................................................................................................................................ 24
Figure 7.1. Four-Position DIP Switch Circuits ...................................................................................................................... 26
Figure 7.2. Four-Position DIP Switch Photograph ............................................................................................................... 26
Figure 7.3. Push Button SW5 Circuit Design ....................................................................................................................... 27
Figure 7.4. Board LEDs ........................................................................................................................................................ 28
Figure 8.1. POT Circuit Design for VMON7 ......................................................................................................................... 31
Figure 8.2. POT Wiper Description ..................................................................................................................................... 31
Figure 8.3. VCC Core Current Monitoring Circuit................................................................................................................ 32
Figure 8.4. PNP Temperature Sensor Circuit ...................................................................................................................... 32
Figure 8.5. NPN Temperature Sensor Circuit ...................................................................................................................... 32
Figure 8.6. ASC LEDs ........................................................................................................................................................... 33
Figure A.1. Title Page .......................................................................................................................................................... 37
Figure A.2. Block Diagram ................................................................................................................................................... 38
Figure A.3. USB to JTAG I/F ................................................................................................................................................. 39
Figure A.4. VERSA Headers (BANK0) ................................................................................................................................... 40
Figure A.5. Arduino Headers (BANK1) ................................................................................................................................ 41
Figure A.6. CrossLink Headers (BANK2) .............................................................................................................................. 42
Figure A.7. Raspberry Pi Header and Others (BANK3, BANK4, BANK5) .............................................................................. 43
Figure A.8. Analog Sense and Control ................................................................................................................................ 44
Figure A.9. Power Decoupling and LEDs ............................................................................................................................. 45
Figure A.10. Power Regulators ........................................................................................................................................... 46
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0
MachXO3-9400 Development Board
Evaluation Board User Guide
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