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MachXO3-9400 Development Board
Evaluation Board User Guide
5
CrossLink Headers
D
U4
CH0_DCK_P
1
CH0_DCK_P
CH0_DCK_N
2
CH0_DCK_N
3
GND
CH0_DATA0_P
4
CH0_DATA0_P
CH0_DATA1_P
CH0_DATA0_N
5
CH0_DATA0_N
CH0_DATA1_N
6
GND
CH0_DATA2_P
7
CH0_DATA2_P
CH0_DATA3_P
CH0_DATA2_N
8
CH0_DATA2_N
CH0_DATA3_N
9
GND
FX_SN
10
SN
FX_SCLK
11
SCLK
+12V
12
PWR_12V
SDA2
13
SDA1
SCL2
14
SCL1
15
GND
CH2_DATA0_P
16
CH2_DATA0_P
CH2_DATA1_P
CH2_DATA0_N
17
CH2_DATA0_N
CH2_DATA1_N
18
GND
CH2_DCK_P
19
CH2_DCK_P
CH2_DCK_N
20
CH2_DCK_N
43
Shield3
44
Shield4
41
Shield1
Hirose - FX12 - 40 Pos
C
DNI
FX_SCLK
0
DNI
R271
MCLK
FX_MOSI
0
DNI
R272
SISPI
FX_MISO
0
DNI
R273
SPISO
FX_SN
0
DNI
R274
CSSPIN
CH0_DATA1_P
CH0_DATA1_N
CSSPIN
RESETN
CH0_DATA0_P
CH0_DATA0_N
B
CH0_DATA2_P
CH0_DATA2_N
CH2_DATA0_P
CH2_DATA0_N
CH2_DCK_P
CH2_DCK_N
0
DNI
R76
MCLK
[5]
AR_SCK_IO13
0
DNI
R77
SPISO
[5]
AR_MISO_IO12
WP#
HOLD#
CH0_DATA3_P
CH0_DATA3_N
CH2_DATA1_P
CH2_DATA1_N
CH0_DCK_P
CH0_DCK_N
0
DNI
R81
SDA1
[3,4,5,6,7]
SDA0
0
DNI
R83
SCL1
[3,4,5,6,7]
SCL0
A
NOTE : 0 OHM RESISTOR SHUOULD BE PLACED
NEAR U3
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
4
VBUS_5V
+3.3V VCC1_8FT
+12V
R153
R152
R154
U5
0
0
0
DNI
DNI
DNI
CH1_DCK_P
21
1
PWR_12-0V
CH1_DCK_P
CH1_DCK_N
22
RESETN
2
RESETN
CH1_DCK_N
23
PWR_5-0V_L
3
PWR_5-0V
GND
24
CH0_DATA1_P
CH1_DATA0_P
4
CH1_DATA0_P
25
CH0_DATA1_N
CH1_DATA0_N
5
CH1_DATA0_N
26
PWR_3-3V_L
6
PWR_3-3V
GND
CH0_DATA3_P
CH1_DATA2_P
27
7
CH1_DATA2_P
CH0_DATA3_N
CH1_DATA2_N
28
8
CH1_DATA2_N
PWR_1-8V_L
29
9
PWR_1-8V
GND
30
FX_MOSI
FX_SN
10
MOSI
SN
31
FX_MISO
FX_SCLK
11
MISO
SCLK
+12V
32
12
PWR_1-8V
PWR_12_0V
33
SDA2
13
GND
SDA1
34
SCL2
14
GND
SCL1
35
15
PWR_3-3V
GND
36
CH2_DATA1_P
CH3_DATA0_P
16
CH3_DATA0_P
37
CH2_DATA1_N
CH3_DATA0_N
17
CH3_DATA0_N
38
18
PWR_5-0V
GND
CH3_DCK_P
39
SDA1
19
SDA
CH3_DCK_P
CH3_DCK_N
40
SCL1
20
SCL
CH3_DCK_N
45
43
Shield5
Shield3
46
44
Shield6
Shield4
42
41
Shield2
+12V
VBUS_5V
+3.3V
VCC1_8FT
Shield1
Hirose - FX12 - 40 Pos
C24
C25
C26
C27
DNI
0.1uF
0.1uF
0.1uF
0.1uF
Note : Speed of the bus, < 2.5ps skew for pairs and
across the bus, traces should be 100 Ohms
Trace match LVDSI* pins between P and N channels as
well as individual pairs.
U3B
AA2
PB5A
AB2
PB5B
V6
PB5C
U6
PB5D
CH1_DCK_P
AA3
AB12
PB7A_CSSPIN
PB29A_PCLKT2_1
CH1_DCK_N
AB3
AA12
PB7B
PB29B_PCLKC2_1
Y4
V13
PB7C
PB29C
W5
U13
PB7D
PB29D
AA4
AB13
SDA2
0
DNI
R71
PB8A
PB30A
AB4
AA13
SCL2
0
DNI
R70
BANK 2
PB8B
PB30B
U7
Y13
PB8C
PB30C
T8
W13
NOTE : 0 OHM RESISTOR SHUOULD BE PLACED
PB8D
PB30D
AA5
T13
NEAR U3
PB10A
PB32A
AB5
T14
PB10B
PB32B
Y5
U14
PB10C
PB32C
Y6
V14
PB10D
PB32D
AA6
AB14
CH1_DATA1_P
PB11A
PB33A
AB6
AA14
CH1_DATA1_N
PB11B
PB33B
W6
Y14
PB11C
PB33C
V7
W14
PB11D
PB33D
CH1_DATA3_P
AA7
AB15
PB13A
PB35A
CH1_DATA3_N
AB7
AA15
PB13B
PB35B
V8
Y15
PB13C
PB35C
U8
W15
PB13D
PB35D
T9
AB16
CH1_DATA0_P
PB16A_MCLK/CCLK
PB38A
U9
AA16
CH1_DATA0_N
PB16B_SO/SPISO
PB38B
V9
V15
PB16C
PB38C
W8
U15
PB16D
PB38D
CH1_DATA2_P
AA8
AB17
PB18A
PB40A
CH1_DATA2_N
AB8
AA17
PB18B
PB40B
Y8
Y17
PB18C
PB40C
W9
V16
PB18D
PB40D
AA9
AB18
CH3_DATA0_P
PB19A
PB41A
AB9
AA18
CH3_DATA0_N
PB19B
PB41B
T10
Y18
VCCIO2
PB19C
PB41C
U10
W17
PB19D
PB41D
CH3_DCK_P
V10
AB19
PB21A
PB43A
CH3_DCK_N
W10
AA19
PB21B
PB43B
Y9
T15
R80
PB21C
PB43C
Y10
U16
PB21D
PB43D
CH3_DATA1_P
AB20
PB44A
AA10
AA20
CH3_DATA1_N
PB22A_PCLKT2_0
PB44B
AB10
Y19
10K
PB22B_PCLKC2_0
PB44C
T11
W18
PB22C
PB44D
U11
AB21
SN
PB22D
PB46A_SN
AA11
AA21
SISPI
0
R82
PB24A
PB46B_SI/SISPI
AB11
V17
PB24B
PB46C
V11
T16
DNI
PB24C
PB46D
Y11
PB24D
Y12
PB27A
T12
PB27B
U12
PB27C
V12
PB27D
XO3L_10K_484CABGA
4
Figure A.6. CrossLink Headers (BANK2)
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
VBUS_5V
+3.3V VCC1_8FT
+12V
R155
R156
R157
0
0
0
DNI
DNI
DNI
21
PWR_12V
22
RESETN
RESETN
23
PWR_5-0V_R
PWR_5-0V
24
CH1_DATA1_P
CH1_DATA1_P
25
CH1_DATA1_N
CH1_DATA1_N
26
PWR_3-3V_R
PWR_3-3V
CH1_DATA3_P
27
CH1_DATA3_P
CH1_DATA3_N
28
CH1_DATA3_N
PWR_1-8V_R
29
PWR_1-8V
30
FX_MOSI
MOSI
31
FX_MISO
MISO
32
PWR_1-8V
33
GND
34
GND
35
PWR_3-3V
36
CH3_DATA1_P
CH3_DATA1_P
37
CH3_DATA1_N
CH3_DATA1_N
38
PWR_5-0V
39
SDA1
SDA
40
SCL1
SCL
45
Shield5
46
Shield6
42
+12V
VBUS_5V
+3.3V
VCC1_8FT
Shield2
C20
C21
C22
C23
0.1uF
0.1uF
0.1uF
0.1uF
SPI FLASH
R68
910
SISPI
0
R72
SDI
[7]
SISPI
SDA0
[3,4,5,6,7]
SCL0
[3,4,5,6,7]
MCLK
250
R74
SCK
[7]
MCLK
WP#
JP8
CSSPIN
2
1
CS#
[7]
CSSPIN
JUMPER
HOLD#
AARDVARK
Connector
JP2
JP2_SCL
1
2
[3]
JP2_SCL
1
2
JP2_SDA
3
4
[3]
JP2_SDA
3
4
SPISO
5
6
5
6
MCLK
7
8
7
8
SS
9
10
9
10
HEADER 5X2
DNI
AR_MOSI_IO11 [5]
AARDVARK
CSSPIN
R161
DNI
0
SN
R160
0
[7]
SN
AR_SS_IO10
R67
DNI
0
[5]
AR_SS_IO10
3
2
1
NOTE : PLACE ALL THE TERMINATION
LVDS RX TERMINATION RESISTORS
RESISTORS ON TOP SIDE AND CLOSE
TO THE U3
CH0_DCK_P
CH0_DATA3_P
CH1_DATA2_P
CH2_DATA1_P
R49
R50
R51
R52
100
100
100
100
CH0_DCK_N
CH0_DATA3_N
CH1_DATA2_N
CH2_DATA1_N
DNI
DNI
DNI
DNI
CH0_DATA0_P
CH1_DCK_P
CH1_DATA3_P
CH3_DCK_P
R53
R54
R55
R56
100
100
100
100
CH0_DATA0_N
CH1_DCK_N
CH1_DATA3_N
CH3_DCK_N
DNI
DNI
DNI
DNI
CH0_DATA1_P
CH1_DATA0_P
CH2_DCK_P
CH3_DATA0_P
R57
R58
R59
R60
100
100
100
100
CH0_DATA1_N
CH1_DATA0_N
CH2_DCK_N
CH3_DATA0_N
DNI
DNI
DNI
DNI
CH0_DATA2_P
CH1_DATA1_P
CH2_DATA0_P
CH3_DATA1_P
R61
R62
R63
R64
100
100
100
100
CH0_DATA2_N
CH1_DATA1_N
CH2_DATA0_N
CH3_DATA1_N
DNI
DNI
DNI
DNI
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
VCCIO2
C28
R65
R66
R69
100nF
10V
U6
10K
10K
10K
5
2
SDO
0
R73
SPISO
SPISO
[7]
SDI
SDO
6
SCK
3
SPI FLASH
WP
1
7
CS
HOLD
S25FL116K0XMFI043
VBUS_5V
+5V_I2C
0
DNI
R78
+5V_SPI
0
DNI
R79
SISPI
SS
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Lattice Semiconductor Applications
http://www.latticesemi.com
http://www.latticesemi.com
http://www.latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Phone (503) 268-8001 -or- (800) LATTICE
Phone (503) 268-8001 -or- (800) LATTICE
Title
Title
Title
CrossLink Headers (BANK2)
CrossLink Headers (BANK2)
CrossLink Headers (BANK2)
Size
Size
Size
Project
Project
Project
C
C
C
MachXO3-9400-Dev-Brd
MachXO3-9400-Dev-Brd
MachXO3-9400-Dev-Brd
Date:
Date:
Date:
Monday, May 22, 2017
Monday, May 22, 2017
Monday, May 22, 2017
2
1
D
C
B
A
4.0
4.0
4.0
Schematic Rev
Schematic Rev
Schematic Rev
Board Rev
Board Rev
Board Rev
B
B
B
Sheet
Sheet
Sheet
6
6
6
of
of
of
10
10
10
FPGA-EB-02004-1.0
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