Aardvark Header (Dni); Figure 5.1. Aardvark Ss Pin Connections; Table 5.9. Aardvark Jp2 Header Pin Connections - Lattice Semiconductor MachXO3-940 User Manual

MachXO3-9400 Development Board
Evaluation Board User Guide
Table 5.8. FX12 U5 Header Pin Connections (continued)
U5 Pin Number
34
35
36
37
38
39
40
Notes:
* Signal is optionally connected to power source through resistor; DNI.
** 12 V power needs external supply from pin 8 of J4.

5.4. Aardvark Header (DNI)

2
The Aardvark I C /SPI Host Adapter is a fast and powerful I
developer to interface a Windows, Linux, or Mac OS X PC through USB to a downstream embedded system
environment and transfer serial messages using the I
The MachXO3-9400 Development Board provides an Aardvark compatible header for customer applications. The I
bus is capable of connecting to a global I

Table 5.9. Aardvark JP2 Header Pin Connections

JP2 Pin Number
1
2
3
4
5
6
7
8
9
10
Caution: VCCIO2 should be 3.3 V when connected to Aardvark I
Pin 9 of the Aardvark header is an SS signal, which is optionally connected to multiple devices or connectors. By default,
it can access Slave SPI in the MachXO3 device as the Master SPI through R160. It can access FX12 header, Raspberry Pi
header and on-board SPI Flash by enabling R161. It can also access the Arduino header by enabling R67.
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
Signal Name
GND
PWR_3-3V*
CH3_DATA1_P
CH3_DATA1_N
PWR_5-0V*
SDA1
SCL1
2
C bus and SPI bus host adapter through USB. It allows a
2
C and SPI protocols.
2
C bus on the board if JP10 is NOT set.
Signal Name
JP2_SCL
—
JP2_SDA
+5V_I2C
SPISO
+5V_SPI
MCLK
SISPI
SS
—

Figure 5.1. Aardvark SS Pin Connections

MachXO3 Ball Location
- —
— -
AB20
AA20
— -
AA11
AB11
MachXO3 Ball Location
2
To I C analog switch U10
GND
2
To I C analog switch U11
To VBUS_5V through R78, DNI
To MachXO3 U9
To VBUS_5V through R79, DNI
To MachXO3 T9
To MachXO3 AA21
Multiple options, as shown in
—
2
C/SPI Host Adapter.
2
C
Figure 5.1.
FPGA-EB-02004-1.0