Table of Contents
Advertisement
5
VCC_CORE
U3E
K10
VCC1
K11
VCC2
K12
VCC3
K13
VCC4
L11
VCC5
L12
VCC6
M11
VCC7
M12
VCC8
D
N10
VCC9
N11
VCC10
N12
VCC11
N13
VCC12
VCCIO5
F3
VCCIO5_1
VCCIO1_1
J8
VCCIO5_2
VCCIO1_2
VCCIO4
K8
VCCIO5_3
VCCIO1_3
VCCIO1_4
L8
VCCIO4_1
VCCIO1_5
M8
VCCIO4_2
VCCIO1_6
M3
VCCIO4_3
VCCIO1_7
VCCIO1_8
VCCIO3
VCCIO1_9
N8
VCCIO3_1
P8
VCCIO3_2
VCCIO2
V3
VCCIO3_3
R9
VCCIO2_1
VCCIO0_1
R10
VCCIO2_2
VCCIO0_2
R11
VCCIO2_3
VCCIO0_3
R12
C
VCCIO2_4
VCCIO0_4
R13
VCCIO2_5
VCCIO0_5
R14
VCCIO2_6
VCCIO0_6
W7
VCCIO2_7
VCCIO0_7
W11
VCCIO2_8
VCCIO0_8
W16
VCCIO2_9
VCCIO0_9
XO3L_10K_484CABGA
VCCIO0
C35
C36
C37
C38
C39
C40
C41
10uF
0.1uF
0.01uF
0.01uF
0.01uF
0.1uF
0.01uF
0.01uF
VCCIO1
B
C45
C46
C47
C48
C49
C50
C51
10uF
0.1uF
0.01uF
0.01uF
0.01uF
0.1uF
0.01uF
0.01uF
VCCIO2
C55
C56
C57
C58
C59
C60
C61
10uF
0.1uF
0.01uF
0.01uF
0.01uF
0.1uF
0.01uF
0.01uF
VCC_CORE
A
C65
C66
C67
C68
C69
C70
C71
10uF
0.1uF
0.01uF
0.01uF
0.01uF
0.1uF
0.01uF
0.01uF
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02004-1.0
4
U3F
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
VCCIO1
GND13
GND14
F20
GND15
J15
GND16
K15
GND17
L15
GND18
M15
GND19
M18
GND20
N15
GND21
P15
GND22
V20
GND23
GND24
GND25
GND26
VCCIO0
GND27
GND28
C7
GND29
C12
GND30
C16
GND31
G10
GND32
G13
GND33
H9
GND34
H11
GND35
H12
GND36
H14
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
C42
C43
C44
C106
GND49
GND50
0.01uF
0.01uF
0.01uF
GND51
GND52
XO3L_10K_484CABGA
C52
C53
C54
C107
0.01uF
0.01uF
0.01uF
VCCIO3
C62
C63
C64
C108
C78
C79
C80
0.01uF
0.01uF
0.01uF
10uF
0.1uF
0.01uF
C72
C73
C74
C75
C76
C77
C105
C82
0.01uF
0.01uF
0.1uF
0.01uF
0.01uF
0.01uF
10uF
4
Figure A.9. Power Decoupling and LEDs
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
A1
A22
B7
B16
C2
C11
E5
E18
F2
F21
H8
H10
H13
H15
J9
J10
J11
J12
J13
J14
K9
K14
K21
L2
LAYOUT LEDs IN A SINGLE ROW
L9
L10
[7]
XLED7
L13
[7]
XLED6
L14
[7]
XLED5
L18
[7]
XLED4
M4
[7]
XLED3
M9
[7]
XLED2
M10
[7]
XLED1
M13
[7]
XLED0
M14
N9
N14
N21
P9
Note : LEDs above are controlled by XO3L I/O Bank 5.
P10
When VCCIO5 is set to a voltage less than 3.3V, observe
P11
P12
all
I/O overdrive requirements.
P13
"MachXO3L sysIO Usage Guide" for more information.
P14
R8
R15
V2
V21
+3.3V
W12
Y7
Y16
R165
R167
AB1
AB22
2.2k
2.2k
R166
R168
2.2k
2.2k
D9
D10
Red
Red
ASC_LED1
ASC_LED2
[8]
ASC_LED[1:6]
[8]
ASC_LED[8:10]
C81
C109
0.01uF
0.01uF
VCCIO4
VCCIO5
C83
C84
C85
C110
C113
C111
C114
0.1uF
0.01uF
0.01uF
0.01uF
10uF
0.1uF
0.01uF
3
MachXO3-9400 Development Board
Evaluation Board User Guide
2
LEDs
+3.3V
R113
R114
R115
R116
R117
R118
1K
1K
1K
1K
1K
1K
D8
D7
D6
D5
D4
D3
Red
Red
Red
Red
Red
Red
Refer to Lattice TN1280
R169
R171
R173
R175
R177
2.2k
2.2k
2.2k
2.2k
2.2k
R170
R172
R174
R176
R178
2.2k
2.2k
2.2k
2.2k
2.2k
D11
D12
D13
D14
D15
Red
Red
Red
Red
Red
ASC_LED3
ASC_LED4
ASC_LED5
ASC_LED6
ASC_LED8
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Lattice Semiconductor Applications
http://www.latticesemi.com
http://www.latticesemi.com
http://www.latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Phone (503) 268-8001 -or- (800) LATTICE
Phone (503) 268-8001 -or- (800) LATTICE
C112
C115
Title
Title
Title
Power Decoupling and LEDs
Power Decoupling and LEDs
Power Decoupling and LEDs
0.01uF
0.01uF
Size
Size
Size
Project
Project
Project
B
B
B
MachXO3-9400-Dev-Brd
MachXO3-9400-Dev-Brd
MachXO3-9400-Dev-Brd
Date:
Date:
Date:
Monday, May 22, 2017
Monday, May 22, 2017
Monday, May 22, 2017
2
1
D
R119
R120
1K
1K
D2
D1
Red
Red
C
R179
R121
2.2k
2.2k
R180
R122
2.2k
2.2k
B
D16
D17
Red
Red
ASC_LED9
ASC_LED10
A
4.0
4.0
4.0
Schematic Rev
Schematic Rev
Schematic Rev
Board Rev
Board Rev
Board Rev
B
B
B
Sheet
Sheet
Sheet
9
9
9
of
of
of
10
10
10
1
45
Advertisement
Table of Contents
