JRC NTG337-EL0 Instruction Manual page 52

Fwa system
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RJ-4 5
TRANS
10 0 B A S E -
T X
Serge protection
TRANS
RJ-4 5
4 p i n
M O JUR A
driver/re ceiver
( t o PC )
IFU-PS
Pow
P ower
Pow
supply
supp ly
supply
conn.
D C - 48 V
con nect or
conn.
Serge protection
AP-IFU
Interface part
R eset
IC
2 .5M Hz
LAYER2
2 5MH z
SW
PHY
MAC
EDC
TRANS TRANS
PHY_RST
L2 SW_RST
(FROM_AP-ASIC)
(FROM_AP-ASIC)
AP - AS I C
RS- 232 C
S D R A M
S D R A M
8 M × 1 6
8 M × 1 6
s e r i a l
E E P R O M
F R O M
3 2 × 8
1 6 M
F R O M
6 4 M
15 .6 25
R T C
MH z
S - CP U
+16V(RFU)
S_R ST
D_ RST
+3.3V(for AP/MODEM-ASIC,IF)
[FR OM_A P-A SIC]
[F ROM_ AP- ASIC ]
+2.5V(for AP-ASIC)
+1.8V(for U-CPU,D-CPU,L2SW)
+1.5V(for MODEM-ASIC)
+5V(for ANALOG ⇒3.3V)
Figure 3-4 AP-IFU Block Diagram
Digital part
20 MH z
TMP
MODE M-A SIC_ RST
SE NS
(FRO M_S -CPU )
L C _ L P F
MO D_ I/ Q
( BA L)
TDD
MOD
TX
D-FIFO
D-FIFO
M OD E M
RX
L VL C NT _T /R
AS I C
S D R A M
8 M × 1 6
DEM
F R O M
D EM _I /Q
1 6 M
( UN BA L)
2 7. 83 MH z
L C _ L P F
CABLELOSSATT(ATT)
TDD_SELECT
D -C P U
+ 3 . 3 _ M O D + 3 . 3 _ D E M
U -C P U
+3. 3_AS IC
ANAL OG
Regu lator
U _RST
Re gulator
[ FROM _AP- ASI C]
3-29
IF part
+ 5 . 0
L C _ B P F
BAL
0/0
UNB
0 /90
× 2
HY B
SW
21 3 .7 5 MH z
0 /90
+ 5 . 0
L C _ B P F
di git al
UNB
0/0
ATT
BAL
[15 dB]
A S K
MO D EM
Regulator
- 3 . 3 V
Serge protection
Regulator
+ 1 6V
+ 5 V
t o R F U
IFU-MAC
to R F U
Co a x a l
C AB L E

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Ntg335-el0Nt337-xl2Ntg337-xl0Ntg337-el2Ntg335-el2

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