JRC NTG337-EL0 Instruction Manual page 61

Figure 4-1 is a block diagram of the WT.
WT-MAC
Interface part
MJ
RS-232
DRV/REC
4P_MJ
MJ
LED DRV
Serge protection
Trans PHY
RJ45
Power supply part
(digital)
+ 3. 3 V_ D ( DI G IT A L )
+ 3. 3 V_ A ( AN A LO G )
DC/DC
+ 1. 5 V( f o r A SI C )
CONV
ｔ
ｏ
S
i
g
n
a
MOD_I/Q
l
p
r
o
c
e
4 27 .5M Hz
s
s
i
n
g DEM_I/Q
p
a
r
t
Signal processing part
X 'T A L
PLL
MOD D/A
2 0 M Hz / 80 M Hz
Conv
MAC TDD
CPU
ASIC
D/A
PON EEP SD
DEM
RST ROM RAM Conv
TEMP FRASH
SENS ROM
WT-IF
ATPC(Analog)
BAL
0/0
UNB
S AW _ BP F
×2
MOD_IC
0/90
21 3.7 5MH z
TRSEL(IF)
SW
HYB ×3
HYB
L C_ B P F SA W _B P F
0/90
AGC(Analog)
UNB
0/0
BAL
S A W_ B P F
DEM_IC
Figure 4-1 WT Block Diagram
TRSEL(RF)
FREQ_CNT(RF)
TRSEL(IF)
t
o
MOD_I/Q(BAL)
I
F
AGC(Analog)
p
AGC(Digital)
a
ATPC(Analog)
r
t
ATPC(Digital)
OFFSET_CNT
DEM_I/Q(UNB)
DC+24V
TRSEL(RF)
FREQ_CNT[CLK/DAT/LE]
ATPC(Digital)
D i el e ct r i c
_ B PF
IF _F req
17 10 MHz
HYB
12 82. 5M Hz
IF _F req
17 10 MHz
I RF
AGC(Digital)
DOWN_CONV
WT_PS
4-38
WT
RF
×2
UP_CONV PA
FREQ_CNT
×n
SW SW
2.4GHz
26G:×5
Synth
TRSEL(RF)
×2
LNA
WG
BPF
Anten na