The High/Low states of the input terminals are detected per clock cycle. When the High states of multiple
terminals are detected, only the input of the terminal with the highest priority becomes valid. The inputs of
terminals with lower priority become invalid. Link the terminals so that multiple signals are not input at the
same time. (Creating a hardware logic where the input to the STOP terminal is detected during the High state
The following shows the priority of the terminals.
1. "PRESET" terminal
2. "STOP" terminal
3. "RUN" terminal
4. "UP" terminal
5. "DOWN" terminal
The RUN terminal holds an event. Thus, when the High states of the PRESET terminal and the RUN terminal
for one clock cycle are detected, the PRESET terminal becomes valid. The RUN terminal becomes valid in
the next clock cycle.
9 CREATING A HARDWARE LOGIC
9.2 Multi Function Counter Block