Mitsubishi Q00JCPU User Manual page 137

Q series, logic
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3
SEQUENCE PROGRAM CONFIGURATION AND
EXECUTION CONDITIONS
(2) Response lag
An output change lags a maximum of one scan behind an input module change
depending on the ON timing of an external contact.
Ladder examples
DX5
55
CPU
(External contact)
module
devices
Diagram 3.62 When DY5E turns ON fastest
External contact
CPU
(External contact)
module
devices
(External load)
Diagram 3.63 When DY5E turns ON slowest
Ladder that turns the DY5E output
DY5E
ON when an DX5 input turns ON.
0
55
ON
OFF
External contact
ON
OFF
DX5
OFF
DY5E
(External load)
0 55
56
END 0
ON
OFF
ON
OFF
DX5
OFF
DY5E
Delay time
(Maximum 1 scan)
3.8 I/O Processing and Response Lag
56
ON
Delay time
55 56
ON
3
3.8.2 Direct mode
1
2
3
4
5
6
7
8
- 72

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