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11 Additional Informations
11.1 Frequently Asked Questions
Q:
Is the SMCS332SpW compatible with the old SMCS332.?
A:
Yes, the link standard IEEE 1355-1995 and ECSS-E-50-12A are compatible, however the old SMCS332 has a
slightly different startup behavior, the SMCS332 must be started first on a link connecting with the
SMCS332SpW.
Q:
The nominal frequency for CLK10 is 10 MHz. Can it be different? What is the effect on the transmission rate?
A:
It can be different, the transmission rate changes in direct proportion to the change of the CLK10 frequency.
However, it is recommended to keep CLK10 at 10 MHz to be conforming to ECSS.
Q:
What is the best way for adding a transfer rate of 5Mbps and still be able to select 10/12.5/25/50/100 Mbps ?
A:
With these settings, transfers at rates down to 6.25 and 3.125 Mbps can be achieved. If the max speed to 80Mbps
then the transmission speed can be selected to 5, 10, 20, 40 and 80 Mbps.
Q:
What is the minimum transmission rate on an SpaceWire link?
A:
SpaceWire defines the max. time between two bits with 850ns, which corresponds to 1.18 Mbit/s.
Q:
Are the outputs of the SMCS332SpW TTL compatible?
A:
Yes; the SMCS332SpW features CMOS outputs and TTL inputs.
Q:
When the SMCS332SpW is connected to a dual port memory, can it monitor the "busy" wire of the DPRAM?
A:
No. External logic is required for that. Due to the mechanism applied in the SMCS, it is not necessary to monitor
the
busy wire when data is flowing via COMI.
Q:
How does the COMI (COmmunication Memory Interface) works in big endian mode?
A:
The COMI works in big endian mode in the same manner as it is described for the HOCI (HOst Control
Interface).
Q:
When in control-by-link mode, can the link used as control link be used to send data to the RAM connected to
the SMCS332SpW?
A:
No, another link must be used for this purpose. See section 4.4.5.
Q:
In control-by-link mode, can I access the link control registers also from the links not working as control link?
A:
Yes, all SMCS332SpW registers can be accessed via the control link. See section 4.4.
Q:
When are the ISR bits reset?
A:
This depends on the width of the host interface. After reset or in control-by-link mode, it is in 8-bit mode. To
reset the ISR bits, do the following: 8-bit mode: Read address 0x04 to 0x07; 16-bit mode: Read address 0x04
and 0x06; 32-bit mode: Read address 0x04.
Q:
What is the use of SMCS332SpW signals CPUR* and SES(3:0) ?
A:
These signals could be used as user defined flags. Examples of possible uses are contained in the
SMCS332SpW
User Manual
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
87 of 131
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