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6.1.4
SMCS332SpW Interrupt Mask Register
All interrupts are masked after reset. The interrupt mask bits are located according to their pendants in the ISR. A '1' written
to the IMR enables the corresponding interrupt in ISR to be activated towards the CPU via the signal HINTR*
6.1.5
Channel specific configuration registers
The channel specific registers are configurable independently. This allows flexible communications with different nodes at
the same time. The following registers are the most important to be set. (x stands for Channel no. 1, 2 or 3)
6.1.5.1
SpaceWire Mode Register (CHx_DSM_MODR)
The basic function of this register is to select the transmit speed.
Bit 3 enables the divider (bit 2 to 0) for transmit bit rate selection.
value
effect
0x00
10 MBit/s
0x0E
lowest transmission bitrate
0x08
highest transmission bitrate
6.1.5.2
COMI Configuration Register (CHx_COMICFG)
This register must be set up if data transfer via COMI is desired. It determines the COMI data bus width for receive and
transmit separately, transmit EOP character or not at the end of a packet and the structure of data storage in the
Communication Memory (refer to chapter "Data Transfer via COMI").
6.1.5.3
Control Register 1 (CHx_CNTRL1)
No configuration has to be made if transmission in transparent mode is desired. For operation with the SMCS332SpW in
protocol mode the respective bits are to set, see chapter 13.
6.1.5.4
SpaceWire Command Register (CHx_DSM_CMDR)
The link can be started by writing a '1' to bit 1 of this register. The corresponding link begins to send NULLs, the first flow
control characters (FCT) will be exchanged after a NULL has been received. Each link can be started or stopped
independently but it should be considered that stopping a link will result in a link disconnect error at the receiving end.
SMCS332SpW
User Manual
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
57 of 131
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