Smcs332Spw Channel 3 Status And Control Registers - Eads Astrium SMCS332SpW User Manual

4.1.4

SMCS332SpW channel 3 status and control registers

Port Width / Register
Address (hex)
32 16 8
50 50 50 CH3_DSM_MODR
51 51 51 CH3_DSM_CMDR
52 52 52 CH3_DSM_STAR
53 53 53 CH3_DSM_TSTR
54 54 54 CH3_ADDR
55 55 55 CH3_RT_ADDR
56 56 56 CH3__PR_STAR
57 57 57
58 58 58 CH3_CNTRL1
59 59 59 CH3_CNTRL2
5A 5A 5A CH3_HTID
5B 5B 5B CH3_HCNTRL
5C 5C 5C CH3_ESR1
5D 5D 5D CH3_ESR2
5E 5E 5E
5F 5F 5F CH3_COMICFG
60 60 60 CH3_TX_SAR
61
62 62 62 CH3_TX_EAR
63
64 64 64 CH3_TX_CAR
65
66 66 66 CH3_TX_FIFO
67 67 67 CH3_TX_EOPB
68 68 68 CH3_RX_SAR
69
6A 6A 6A CH3_RX_EAR
6B
6C 6C 6C CH3_RX_CAR
6D
6E 6E 6E CH3_RX_FIFO
6F 6F 6F CH3_STAR
SMCS332SpW
User Manual
Function
channel 3 DSM mode Register
channel 3 DSM command Register
channel 3 DSM status Register
channel 3 DSM test Register
channel 3 address Register
channel 3 Route address Register
channel 3 Protocol Status Register
reserved
channel 3 control Register 1
channel 3 control Register 2
channel 3 Header Transaction ID byte
channel 3 Header control byte
channel 3 detailed error source register 1
channel 3 detailed error source register 2
reserved
channel 3 COMI configuration register
channel 3 transmit Start Address Register
channel 3 transmit End Address Register
channel 3 transmit Current Address Register
channel 3 transmit FIFO
channel 3 transmit EOP Bit Register
channel 3 receive Start Address Register
channel 3 receive End Address Register
channel 3 receive Current Address Register
channel 3 receive FIFO
channel 3 Status Register
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 21 of 131
Reset Access
Value
(hex)
00 r / w
00 r / w
00 r / w
00 r / w
00 r / w
00 r / w
04 r / w
00 ro
00 r / w
00 r / w
00 ro
00 ro
00 r / w
00 r / w
00 ro
00 r / w
00 r / w
00 r / w
00 ro
00 wo
00 wo
00 r / w
00 r / w
00 ro
xxxxxxxx ro
01 ro