Smcs332Spw Channel 2 Status And Control Registers - Eads Astrium SMCS332SpW User Manual

4.1.3

SMCS332SpW channel 2 status and control registers

Port Width / Register
Address (hex)
32 16 8
30 30 30 CH2_DSM_MODR
31 31 31 CH2_DSM_CMDR
32 32 32 CH2_DSM_STAR
33 33 33 CH2_DSM_TSTR
34 34 34 CH2_ADDR
35 35 35 CH2_RT_ADDR
36 36 36 CH2_PR_STAR
37 37 37
38 38 38 CH2_CNTRL1
39 39 39 CH2_CNTRL2
3A 3A 3A CH2_HTID
3B 3B 3B CH2_HCNTRL
3C 3C 3C CH2_ESR1
3D 3D 3D CH2_ESR2
3E 3E 3E
3F 3F 3F CH2_COMICFG
40 40 40 CH2_TX_SAR
41
42 42 42 CH2_TX_EAR
43
44 44 44 CH2_TX_CAR
45
46 46 46 CH2_TX_FIFO
47 47 47 CH2_TX_EOPB
48 48 48 CH2_RX_SAR
49
4A 4A 4A CH2_RX_EAR
4B
4C 4C 4C CH2_RX_CAR
4D
4E 4E 4E CH2_RX_FIFO
4F 4F 4F CH2_STAR
SMCS332SpW
User Manual
Function
channel 2 DSM mode Register
channel 2 DSM command Register
channel 2 DSM status Register
channel 2 DSM test Register
channel 2 address Register
channel 2 Route Address Register
channel 2 Protocol Status Register
reserved
channel 2 control Register 1
channel 2 control Register 2
channel 2 Header Transaction ID byte
channel 2 Header control byte
channel 2 detailed error source register 1
channel 2 detailed error source register 2
reserved
channel 2 COMI configuration register
channel 2 transmit Start Address Register
channel 2 transmit End Address Register
channel 2 transmit Current Address Register
channel 2 transmit FIFO
channel 2 transmit EOP Bit Register
channel 2 receive Start Address Register
channel 2 receive End Address Register
channel 2 receive Current Address Register
channel 2 receive FIFO
channel 2 Status Register
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 20 of 131
Reset Access
Value
(hex)
00 r / w
00 r / w
00 r / w
00 r / w
00 r / w
00 r / w
04 r / w
00 ro
00 r / w
00 r / w
00 ro
00 ro
00 r / w
00 r / w
00 ro
00 r / w
00 r / w
00 r / w
00 ro
00 wo
00 wo
00 r / w
00 r / w
00 ro
xxxxxxxx ro
01 ro