Smcs332Spw Channel 1 Status And Control Registers - Eads Astrium SMCS332SpW User Manual

4.1.2

SMCS332SpW channel 1 status and control registers

Port Width / Register
Address (hex)
32 16 8
10 10 10 CH1_DSM_MODR
11 11 11 CH1_DSM_CMDR
12 12 12 CH1_DSM_STAR
13 13 13 CH1_DSM_TSTR
14 14 14 CH1_ADDR
15 15 15 CH1_RT_ADDR
16 16 16 CH1_PR_STAR
17 17 17
18 18 18 CH1_CNTRL1
19 19 19 CH1_CNTRL2
1A 1A 1A CH1_HTID
1B 1B 1B CH1_HCNTRL
1C 1C 1C CH1_ESR1
1D 1D 1D CH1_ESR2
1E 1E 1E
1F 1F 1F CH1_COMICFG
20 20 20 CH1_TX_SAR
21
22 22 22 CH1_TX_EAR
23
24 24 24 CH1_TX_CAR
25
26 26 26 CH1_TX_FIFO
27 27 27 CH1_TX_EOPB
28 28 28 CH1_RX_SAR
29
2A 2A 2A CH1_RX_EAR
2B
2C 2C 2C CH1_RX_CAR
2D
2E 2E 2E CH1_RX_FIFO
2F 2F 2F CH1_STAR
SMCS332SpW
User Manual
Function
channel 1 DSM mode Register
channel 1 DSM command Register
channel 1 DSM status Register
channel 1 DSM test Register
channel 1 address Register
channel 1 Route Address Register
channel 1 Protocol Status Register
reserved
channel 1 control Register 1
channel 1 control Register 2
channel 1 Header Transaction ID byte
channel 1 Header control byte
channel 1 detailed error source register 1
channel 1 detailed error source register 2
reserved
channel 1 COMI configuration register
channel 1 transmit Start Address Register
channel 1 transmit End Address Register
channel 1 transmit Current Address Register
channel 1 transmit FIFO
channel 1 transmit EOP Bit Register
channel 1 receive Start Address Register
channel 1 receive End Address Register
channel 1 receive Current Address Register
channel 1 receive FIFO
channel 1 Status Register
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 19 of 131
Reset Access
Value
(hex)
00 r / w
00 r / w
00 r / w
00 r / w
00 r / w
00 r / w
04 r / w
00 ro
00 r / w
00 r / w
00 ro
00 ro
00 r / w
00 r / w
00 ro
00 r / w
0000 r / w
0000 r / w
0000 ro
-- wo
-- wo
0000 r / w
0000 r / w
0000 ro
xxxxxxxx ro
01 ro