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4.2.5
Time Code Registers
4.2.5.1
Time Code Control Register (TIME_CNTRL)
- address:
- data width:
- access mode:
- reset value:
Bit
Description
1:0
Interrupt control bits:
00 =
No interrupt signal to the interrupt controller.
01 =
enable the internal interrupt signal generation to the interrupt controller only for a correct received
TIME CODE character received from the SpaceWire links.
10 =
enable the internal interrupt signal generation to the interrupt controller for all received
TIME CODE characters.
11 =
enable the internal interrupt signal generation to the interrupt controller for a false
TIME CODE character received from the SpaceWire links.
see also interrupt bit in ISR Byte 3, bit 6.
2
Time code value register control bit:
0 =
overwrite of the time code value register with a received time code is enabled.
1 =
No overwrite of the time code value register with a received time code.
3
TIME_CODE_SYNC signal control bit0:
0 =
The TIME_CODE_SYNC signal is disabled.
1 =
A falling edge of the TIME_CODE_SYNC input signal sends the time code register value over the
SpaceWire links.
4
TIME_CODE_SYNC signal control bit1:
0 =
No increment of the time code value register
1 =
A falling edge of the TIME_CODE_SYNC input signal increments the time code register
value by 1.
5
Status: time code character received on SpaceWire link 1.
Only read, reset after read.
6
Status: time code character received on SpaceWire link 2.
Only read, reset after read.
7
Status: time code character received on SpaceWire link 3.
Only read, reset after read.
4.2.5.2
Time Code Value Register (TIME_CODE)
- address:
- data width:
- access mode:
- reset value:
Bit
Description
7:0
Time code value register:
SMCS332SpW
User Manual
0x78
8 bit, D7:0
D4:0: read / write
D7:5: read only
0x00
0x79
8 bit, D7:0
read / write
0x00
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
42 of 131
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