Interrupt Mask Register (Imr); Comi Chip Select0 Boundary Register (Comi_Cs0R); Comi Arbitration Control Register (Comi_Acr) - Eads Astrium SMCS332SpW User Manual

1. read always all bytes
2. read first byte 0, last byte 3
3. when Byte 3 is read, the signal HINTR* will be deactivated for a minimum of two CLK cycles and all bits in
the ISR will be cleared.
Note that the ISR will be latched when reading Byte 0. Only the interrupts flagged at that time will be reset when reading
Byte 3. This makes sure that no interrupts will be lost that happen to be raised in the time between reading Byte 0 and Byte
3.
4.2.1.5

Interrupt Mask Register (IMR)

- address:
- data width:
- access mode:
- reset value:
All interrupts are masked after reset. A '1' written to the IMR enables the corresponding interrupt source in register ISR
to activate the interrupt signal HINTR*.
4.2.1.6

COMI Chip Select0 Boundary Register (COMI_CS0R)

- address:
- data width:
- access mode:
- reset value:
The communication memory address space is divided into two banks. Each bank has a separate memory select pin
CMCS0* and CMCS1*.
The upper COMI address signals CMADR15 - 8 are compared with the value of COMI_CS0R. Bank 0 starts at address
0x0000 until [COMI_CS0R * 256 + 255].
IF 0x0000 <= CMADR <= (COMI_CS0R * 0x100) + 0xFF THEN
CMCS0* is active ELSE
CMCS1* is active.
Example: COMI_CS0R = 0x3F.
Address 0x0000 -0x3FFF => CMCS0* is active.
Address 0x4000 -0xFFFF => CMCS1* is active
4.2.1.7

COMI Arbitration Control Register (COMI_ACR)

- address:
- data width:
- access mode:
- reset value:
Signal COCI is an input pin that requests access from the other SMCS332SpW to the communication memory bus.
When COCI is asserted, the SMCS332SpW COMI interface completes the current access, places the interface in a high-
impedance state and then deasserts the output signal COCO to indicate to the requesting SMCS332SpW that it is no longer
driving the COMI bus.
After [COMI_ACR - 1] CLK cycles and when the SMCS332SpW COMI needs the bus for further access to the
communication memory, the SMCS332SpW asserts the COCO pin (connected with the COCI pin of the other
SMCS332SpW) .
COMI_ACR = wait time between two accesses.
SMCS332SpW
User Manual
0x08 - 0x0B
32 bit, D31:0
read / write
0x00000000
0x0C
8 bit, D7:0
read / write
0xFF
0x0E
4 bit, D3:0
read / write
0x08
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 27 of 131