Pll Filter; Power And Ground Guidelines - Eads Astrium SMCS332SpW User Manual

8.4

PLL Filter

The pin PLLOUT should be connected as shown below:
Values for V = + 5 V ± 0.5V
CC
R1 = 1,8kΩ ± 5%, ¼W
C1 = 33pF, ± 5%, 200V
C2 = 820pF, ± 5%, 200V
Values for V = + 3.3 V ± 0.3V
CC
R1 = 2,0kΩ ± 5%, ¼W
C1 = 33pF, ± 5%, 200V
C2 = 760pF, ± 5%, 200V
8.5

Power and Ground Guidelines

To achieve its fast cycle time, the SMCS332SpW is designed with high speed drivers on output pins. Large peak currents
may pass through a circuit board's ground and power lines, especially when many output drivers are simultaneously charging
or discharging their load capacitances. These transient currents can cause disturbances on the power and ground lines. To
minimize these effects, the SMCS332SpW provides separate supply pins for its internal logic and for its external drivers.
All GND pins should have a low impedance path to ground. A ground plane is required in SMCS332SpW systems to reduce
this impedance, minimizing noise.
The VCC pins should be bypassed to the ground plane using approximately 10 high-frequency capacitors (0.1 µF ceramic).
Keep each capacitor's lead and trace length to the pins as short as possible. This low inductive path provides the
SMCS332SpW with the peak currents required when its output drivers switch. The capacitors' ground leads should also be
short and connect directly to the ground plane. This provides a low impedance return path for the load capacitance of the
SMCS332SpW output drivers.
The following pins must have a capacitor: 20, 78, 129, and 155. The remaining capacitors should be distributed equally
around the SMCS332SpW.
SMCS332SpW
User Manual
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 69 of 131