Table of Contents
Advertisement
Before starting with transmission the channel must be configured for proper operation. Besides general SMCS332SpW
configuration (see chapter SMCS332SpW initialization) at least the following channel specific registers must be set:
Register
CHx_DSM_MODR
CHx_DSM_CMDR
CHx_COMICFG
The Channel Mode Register is basically used to select the transmit bitrate of the link. Then the link can be started by setting
up the Channel Command Register. No data is transmitted yet, but the link sends NULL's and exchanges Flow Control
Tokens with the opposite node (if started as well).
The Channel COMI Configuration Register determines the word width of the COMI data bus basically. Furthermore it
configures whether one or more packets fit into one Communication Memory segment. In the first case the SMCS stops the
RX-address generation after receiving an EOP/EEP and for the reception of another packet the receive channel must be set
up again. In the second case the packets are appended and the SMCS332SpW only signals that the end of the segment is
reached (RX generator finished). The CPU/User must have the knowledge to separate the packets itself.
Example #1:
Link no.1 shall transmit two packets of 16 words ą 32 bit with the maximum bit rate. The same link shall be configured to
receive one packet of up to 64 words ą 16 bit. Link no.2 shall collect 32 bit word packets in the COMI segment without
signaling reception of every packet. The transfers run via the COMI in little endian mode (default).
The Communication Memory is segmented in three parts.
The excerpt of a Pseudo C-code looks like this:
/* init */
ch1_rx_int_occured = 0;
ch1_tx_int_occured = 0;
ch2_rx_int_occured = 0;
/* usage: smcs_reg_write(SMCS base address, register address, value) */
/* configure COMI */
/* Channel 1:
*
32 bit words transmit port followed by EOP,
*
16 bit receive port, stop RX generator after EOP reception,
*
no sign expand
*/
smcs_reg_write(SMCS, CH1_COMICFG, 0x13);
/* Channel 2: 32 bit word receive port, no RX generator stop after EOP reception,
sign expand
*/
smcs_reg_write(SMCS, CH2_COMICFG, 0x70);
/* set interrupt mask (only access on SMCS_IMR0 with 32 bit HOCI) */
/* disable <CH1 TX generator finished>, <CH1 RX EOP/EEP received>,
SMCS332SpW
User Manual
– All Rights Reserved – Copyright per DIN 34 –
Function
Channel Mode Register
Channel Command Register
Channel COMI Configuration Register
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
59 of 131
* no
Advertisement
Table of Contents
