Channel 1 Transmit Fifo (Ch1_Tx_Fifo); Channel 1 Transmit Eop Bit Register (Ch1_Tx_Eopb); Channel 1 Receive Start Address Register (Ch1_Rx_Sar) - Eads Astrium SMCS332SpW User Manual

Bit Description
7:0 lower byte of the current address
Byte 1 at address 0x25: (only in 8 bit mode of the HOCI data port):
Bit Description
7:0 upper byte of the current address
4.2.2.18

Channel 1 Transmit FIFO (CH1_TX_FIFO)

- address:
- data width:
- access mode:
- reset value:
Beside the communication memory the host processor can send data over the transmit FIFO interface.
The FIFO data width is equal to the HOCI data port width.
The FIFO has a size of 32 bytes. The host processor can control the data transmission with bits 6 and 7 of the interrupt
status register (ISR) or with the status bits 0 and 1 of the channel 1 status register (CH1_STAR).
At the end of the packet the host processor has to send an EOP character with register CH1_TX_EOPB.
4.2.2.19

Channel 1 Transmit EOP Bit Register (CH1_TX_EOPB)

- address:
- data width:
- access mode:
- reset value:
For data transfer over the transmit FIFO, the host processor has to send the EOP character at the end of the packet.
If the host processor sets bit 0 or 1 or both, the SMCS332SpW sends an EOP character at the end of the packet.
Bit Description
0 send an EOP character
1 send an EOP character
7:2 always '0' / reserved
4.2.2.20

Channel 1 Receive Start Address Register (CH1_RX_SAR)

- address:
- data width:
- access mode:
- reset value:
The value of CH1_RX_SAR shows the start address of an area in the communication memory, where the received data shall
be written.
Byte 0 at address 0x28:
SMCS332SpW
User Manual
0x26
8/16/32 bit, D31:0
write only
n/a
0x27
2 bit, D1:0
write only
n/a
0x28 - 0x29
16 bit, D15:0
read / write
0x0000
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EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 39 of 131