Table of Contents
Advertisement
2.5
PPU Functional Description
Since the Protocol Processing Unit (PPU) determines a major part of the SMCS332SpW functionality, the principal blocks of
the PPU and their function are described here. This functionality is provided for every SpaceWire channel of the
SMCS332SpW.
•
Protocol Execution Unit: This unit serves as the main controller of the PPU block. It receives the character from the
SpaceWire cell and interprets (in protocol mode) the four header data characters received after an EOP control
character. If the address field matches the link channel address and the command field contains a valid command
then forwarding of data into the receive FIFO is enabled. If the command field contains a "simple control
command" then the execution request is forwarded to the command execution unit.
The protocol execution unit also enables forwarding of header data characters to the acknowledge generator and
provides an error signal in case of address mismatch, wrong commands or disabled safety critical "simple control
commands".
The protocol execution unit is disabled in "transparent" or "wormhole routing" operation mode.
•
Receive, Transmit, Acknowledge: the transmit and receive FIFOs decouple the SpaceWire link related operations
from the SMCS332SpW related operations in all modes and such allows to keep the speed of the different units
even when the source or sink of data is temporarily blocked.
In the protocol mode a further FIFO (acknowledge FIFO) is used to decouple sending of acknowledges from
receiving new data when the transmit path is currently occupied by a running packet transmission.
•
Command Execution Unit: This unit performs activating resp. deactivating of the CPU reset and the specific
external signals and provides the capability to reset one or all links inside the SMCS332SpW, all actions requested
by the decoded commands from the protocol execution unit.
The unit contains a register controlling the enable/disable state of safety critical commands which is set into the
'enable' state upon command request and which is reset after a safety critical command has been executed.
The CPU reset and the specific external signals are forwarded to the Protocol Command Interface (PRCI).
2.6
Fault Tolerance
The SpaceWire standard specifies low level checks as link disconnect, credit value, sequence and parity at token level. The
SMCS332SpW provides, through the Protocol Processing Unit, features to reset a link or all links inside the SMCS332SpW,
to reset the local CPU or to send special signals to the CPU commanded via the links.
Additionally it is possible to enable a checksum coder/decoder to have fault detection capabilities at packet level.
2.7
Software Support
The SMCS332SpW is supported by VSPWorks from Wind River, a commercially available distributed real-time kernel. It is
a multi-tasking as well as a multi-processor Operating System. The main goals are to enable programming at a higher level to
configure and to perform communication and to administer the tasks on a board with multiple processes running in parallel.
The VSPWorks kernel supports multiple processors and application specific chips, e.g. the SHARC, ADSP21020,
TMS320C40, SPARC ERC32 etc. Thus it is possible to run a heterogeneous multiprocessor system with a single Operating
System without consideration of the hardware platform.
SMCS332SpW
User Manual
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
12 of 131
Advertisement
Table of Contents
