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After a critical simple command has been executed, the simple command execution state is immediately changed from
'enable' to 'disable'. This assures that every critical simple command execution must be preceded by a 'enable' command.
Complex Control Commands
The same two step procedure as for simple control commands is applied to complex control commands with the difference
that the status of enabling a complex command is not stored in the link status register. Since it is assumed that the complex
commands are executed by SW running on the CPU of a node, the status of complex commands is kept in a SW register and
can be read by the 'read status of complex command enable switch' complex command.
13.4.4
Reset Commands
Reset Link Interface HW
Provided that safety critical command execution has been enabled, the execution of this command is performed immediately
after correct reception of the command and the EOP marker. Due to the immediate execution, no acknowledge packet is sent.
The command has the following results:
Link Frontend
After receiving a reset link channel command, the frontend performs the following actions analog to the SpaceWire DS-SE
link procedures.
A auto-restart procedure is required so that the node requesting a 'reset link channel' command can assume that the other
node is again operating after a certain amount of time after the 'reset link channel' command.
This requires that the link frontend which has executed the 'reset' command either automatically starts to transmit FCTs and
NULL characters after having received tokens from the other node or that the node CPU observes reception of tokens after
link interface reset and then enables the link interface to restart with transmission.
Channel Status Register
The status register is cleared (reset) but one bit is set indicating that the link channel has started up from an externally
commanded reset.
Node CPU Interface
The interface configurations are not modified and the interface MUST be left operational but a signal is generated indicating
to the CPU that an externally commanded reset has occurred. (This may be implemented as a specific signal or as an
interrupt/read status register sequence)
Memory Interface / Transmission Path
Any currently running transmission at the link to be reset is interrupted immediately by the reset command. Since the state
of transmission cannot be restored, the transmission path is completely reset including clearing of any transmission related
configuration register of the memory interface and clearing of intermediate storage containing data already read for
transmission from communication memory but not yet forwarded to the link frontend. The transmission path must be
completely reconfigured by the CPU after this kind of reset.
Memory Interface / Reception Path
The reception path is left unchanged, especially all intermediate storage containing data received previously but not yet
forwarded to the working memory of the node. The reception path can be left unchanged since it can be assumed that the last
data packet previous to this reset command was received correctly, otherwise this reset command would have not been
SMCS332SpW
User Manual
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
120 of 131
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