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Eads Astrium SMCS332SpW Manuals
Manuals and User Guides for Eads Astrium SMCS332SpW. We have
1
Eads Astrium SMCS332SpW manual available for free PDF download: User Manual
Eads Astrium SMCS332SpW User Manual (131 pages)
interface between three SpaceWire links
Brand:
Eads Astrium
| Category:
Recording Equipment
| Size: 1.3 MB
Table of Contents
Table of Contents
3
1 Scope and Objectives
7
Doc No: SMCS_ASTD_UM_100
7
Issue
7
List of Applicable Documents
7
Reference Documents
7
List of Abbreviations
8
2 Introduction
9
Interfaces
10
Operation Modes
11
Smcs332Spw Control by Spacewire Link
11
Wormhole Routing
11
PPU Functional Description
12
Fault Tolerance
12
Software Support
12
Application
13
Smcs332Spw Connected with the Old SMCS332
13
3 The Spacewire Link
14
Data/Strobe Spacewire Signals
14
Character Level Flow Control
15
Link Speeds
16
Errors on Links
16
Spacewire State on Start up
17
Link Connections
17
4 Register Set
18
Register Address Map
18
Smcs332Spw Status and Control Registers
18
Smcs332Spw Channel 1 Status and Control Registers
19
Smcs332Spw Channel 2 Status and Control Registers
20
Smcs332Spw Channel 3 Status and Control Registers
21
Smcs332Spw GPIO Control Registers
22
Time Code Control Registers
22
Register Description
23
General SMCS Registers
23
Smcs332Spw Interface Control Register (SICR)
23
Transmit Bitrate Base Register (TRS_CTRL)
23
Route Control Status Register (RT_CTRL)
24
Interrupt Status Register (ISR)
24
Interrupt Mask Register (IMR)
27
COMI Chip Select0 Boundary Register (COMI_CS0R)
27
COMI Arbitration Control Register (COMI_ACR)
27
PRCI Register (PRCIR)
28
Channel 1 Registers
29
Channel 1 Spacewire Mode Register (CH1_DSM_MODR)
29
Channel 1 Spacewire Command Register (CH1_DSM_CMDR)
29
Smcs332Spw User Manual
30
Doc No: SMCS_ASTD_UM_100
30
Issue
30
Channel 1 Link Spacewire Status Register (CH1_DSM_STAR)
30
Channel 1 Spacewire Test Register (CH1_DSM_TSTR)
31
Channel 1 Address Register (CH1_ADDR)
31
Channel 1 Route Address Register (CH1_RT_ADDR)
32
Channel 1 Protocol Status Register (CH1_PR_STAR)
32
Channel 1 Control Register 1 (CH1_CNTRL1)
33
Channel 1 Control Register 2 (CH1_CNTRL2)
34
All Rights Reserved – Copyright Per DIN
34
Channel 1 Header Transaction ID (CH1_HTID)
35
Channel 1 Header Control Byte (CH1_HCNTRL)
35
Channel 1 Error Source Register 1 (CH1_ESR1)
35
Channel 1 Error Source Register 2 (CH1_ESR2)
36
Channel 1 COMI Configuration Register (CH1_COMICFG)
36
Channel 1 Transmit Start Address Register (CH1_TX_SAR)
37
Channel 1 Transmit End Address Register (CH1_TX_EAR)
38
Channel 1 Transmit Current Address Register (CH1_TX_CAR)
38
Channel 1 Transmit FIFO (CH1_TX_FIFO)
39
Channel 1 Transmit EOP Bit Register (CH1_TX_EOPB)
39
Channel 1 Receive Start Address Register (CH1_RX_SAR)
39
Channel 1 Receive End Address Register (CH1_RX_EAR)
40
Channel 1 Receive Current Address Register (CH1_RX_CAR)
40
Channel 1 Receive FIFO (CH1_RX_FIFO)
41
Channel 1 Status Register (CH1_STAR)
41
Channel 2 Registers
41
Channel 3 Registers
41
Time Code Registers
42
Time Code Control Register (TIME_CNTRL)
42
Time Code Value Register (TIME_CODE)
42
5 Smcs332Spw Modes
44
HOCI Data Transfer
44
COMI Data Transfer
45
COMI Arbitration
45
Control by Link
48
Selecting Remote Mode
48
Determination of the Control Link
48
Protocol and Commands
48
Host Data Bus / GPIO Port
49
Restrictions
49
Wormhole Routing
49
Overview
49
Wormhole Routing on Smcs332Spw
50
Routing Implementation on Smcs332Spw
50
Smcs332332Spw Routing Examples
51
Header Bytes Generation
51
Header Field Control Bit
51
Routing and Checksum Generation
53
Time Code Interface
54
Smcs33Spw Transmit Time Code
54
Smcs332Spw Receive Time Code
55
Smcs332Spw Version Control
55
6 Programming and Operation Modes
56
Smcs332Spw Initialization
56
Smcs332Spw Interface Control Register
56
Transmit Bitrate Register (TRS_CTRL)
56
Smcs332Spw User Manual
56
Doc No: SMCS_ASTD_UM_100
56
Issue
56
Smcs332Spw Interrupt Status Register (ISR)
56
Smcs332Spw Interrupt Mask Register
57
Channel Specific Configuration Registers
57
Spacewire Mode Register (Chx_Dsm_Modr)
57
COMI Configuration Register (Chx_Comicfg)
57
Control Register 1 (Chx_Cntrl1)
57
Spacewire Command Register (Chx_Dsm_Cmdr)
57
Data Transfer Via COMI
58
Data Transfer Via HOCI
61
Special Behaviour in Case of Spacewire Link Error
62
7 Signal Description
64
8 Electrical Specifications
67
Absolute Maximum Ratings
67
DC Electrical Characteristics
67
Power Consumption
68
PLL Filter
69
Power and Ground Guidelines
69
9 Timing Parameters
70
Clock Signals
70
Reset
72
Host Read
73
Host Write
75
COMI Read
77
COMI Write
78
COMI Arbitration
79
CPUR, SES, Interrupt
80
Links
81
Test Port (JTAG)
82
10 Mechanical Data
84
Package Dimensions
84
Pin Assignment
85
11 Additional Informations
87
Frequently Asked Questions
87
BSDL File for the Smcs332Spw
90
Issue: 1.4
100
Issue: 1.4
101
Issue: 1.4
102
Issue: 1.4
103
Issue: 1.4
104
Issue: 1.4
109
12 Handling Empty Packets
110
Description
110
Issue: 1.4
111
Issue: 1.4
112
Workaround
113
13 Simple Interprocessor Communication Protocol Specification
114
Application Scenario
114
Assumptions about the Environment
115
Service Specification
115
Transport of Data between Two Nodes
115
Execution of Control Commands
116
Simple Control Commands
116
Complex Control Commands
117
Procedure Rules
118
Acknowledgements
118
Access to Command Signal Output Ports
119
Safety Critical Commands
119
Reset Commands
120
Shutdown Link Channel Operation / Restart Link Channel Operation
121
Read of Link Interface Status Register
121
Encoding (Format) of Transactions
122
Header and EOP Coding
122
Control Word Coding Specification
122
Issue: 1.4
123
Link Interface Status Register Encoding
124
Data Transfer Type Transactions
125
Read Link Interface Status Register Transaction
126
Enable Command Execution Transaction
127
Critical Simple Command Execution Transaction
128
Glossary
129
14 Differences between the Smcs332Spw and the Old SMCS332
130
Summary of Changed/Modified/Added Registers or Register Bits
130
Pin Modifications
131
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