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Description
HSEL*, HWR* and SMCSADR and HADR setup before CLK high
HADR, SMCSADR hold after HSEL* or HWR* high
HWR* pulse width high
HACK low after HWR*, HSEL* active and SMCSADR valid
HACK high after HSEL* and HWR* and SMCSADR = SMCSID
HACK disable after HWR* or HSEL* inactive or SMCSADR invalid
3)
HDATA setup before HSEL* or HWR* high or SMCSADR ≠
SMCSID
HDATA hold after HWR* or HSEL* inactive or SMCSADR invalid
Notes:
1)
To achieve the above timing (t
to the HOCI port (e.g. by a NOP or any other instruction between two HOCI writes), depending on the type and clock
frequency of the CPU.
2)
Signal HACK active when HRD* low and HSEL* low and SMCSADR = SMCSID
3)
Signal HACK disable when HRD* high or HSEL* high or SMCSADR ≠ SMCSID
SMCS332SpW
User Manual
1)
) without hardware, it may be necessary to avoid two subsequent write write accesses
HWWH
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
Updated: 9-Sep-2006
Page:
Symb.
Min.
t
7
HWSU
t
0
HWAH
t
1 * t
HWWH
CLK
6
2)
t
HWACKL
t
1 * t
HWACKH
CLK
5
t
HWACKA
t
7
HWDSU
t
0
HWDH
1.4
76 of 131
Max.
Unit
ns
ns
+
ns
23
ns
+
2.5 * t
+
ns
CLK
41
24
ns
ns
ns
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