Table of Contents
Advertisement
13.2 Assumptions about the Environment
The protocol specified here is intended to work on top of the SpaceWire link protocol. This covers e.g. link startup, low level
error handling, low level flow control, timeouts, routing provisions and the like.
This protocol assumes a link interface HW implementation based on a front-end which handles all SpaceWire related issues
and a backend providing resources to interpret this protocol and perform the required actions e. g. in case of commands or
acknowledges. The link interface is controlled (at least for configuration purposes) by the CPU of a node.
It is further assumed that within the protocol specific HW circuitry buffer storage (FIFOs) exist in addition to the receive and
transmit FIFOs provided by the SpaceWire link frontend circuitry. These additional FIFOs are large enough to decouple (at
least to a certain extent) the transmission speed on the SpaceWire links from the transfer speed between the node's
communication memory and the link interface. If the receive FIFO is full, reception of further tokens is stalled utilizing the
SpaceWire link low level flow control mechanism.
If more than one link interface HW is integrated on one chip the different link channels can share the interfaces for the
protocol's control commands, for the data transferred between the node's communication memory and the links and the
control interface provided to enable control by the CPU.
The transmission of data and command is structured into packets. Although this protocol does not limit the maximum packet
length, it is recommended that the packet length is kept short to decrease latency and to avoid blocking of links due to long
packets.
Since the protocol is intended to be used in HW implementations housed in shielded boxes with a "clean" electrical
environment inside, no additional error protection/checking is performed on top of the parity checking already provided by
the SpaceWire links. However, it is expected that the SW kernel running on the nodes of the system provides a certain set of
control functions.
The protocol supports routing and assumes Inmos C104 like routing networks with one byte header and without header
deletion. The protocol provides a structure to enable routing but does not define how the routing is actually performed and
how certain network events (e.g. transmission errors or change of transmission speed) are propagated via the router.
13.3 Service Specification
Based on this protocol, data characters and simple system control commands are transported between nodes of a
multiprocessor system. The protocol does interpret control commands if they are coded as specified for 'simple control
commands' in para. 5. Data transferred via the link is not interpreted by the protocol but exchanged transparently with the
CPU of a node. This implies that every acknowledgement required by the content of the data must be performed by SW (a
higher level communication protocol) running on the CPU.
Since this protocol does not interpret the data transferred between nodes, specific functions and commands in addition to the
ones specified in the description below can be freely embedded within the data.
The protocol is based on a packet communication structure, it allows a full duplex transfer of data and commands.
13.3.1
Transport of data between two nodes
The transaction level protocol described here provides transport of data structured into packets between the endpoints of a
communication link. It does not interpret the data. It is up to other (here not specified) parts of a higher transaction level
protocol (e.g. running on the CPU of the node) to control the transfer data from the link interface to buffers in the working
memory of a node and to interpret the data.
The SpaceWire links which are used for the implementation of the low levels of the protocol transports data in pieces of 'data
characters' consisting of 8 bits. It is also the smallest entity of data which is covered by the data transport service of this
protocol. It is up to an implementation into which higher datastructures the 8 bit entity is organized.
Data transfer between two nodes is basically acknowledged by this protocol on a packet by packet basis. This acknowledge
covers the correct reception of data up to the EOP 'end of packet marker' and the storage of the data into the link interface's
receive FIFO. The acknowledge provided here does not cover the correct transfer of data from the link interface HW to the
SMCS332SpW
User Manual
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
115 of 131
Advertisement
Table of Contents
