Data Transfer Via Comi - Eads Astrium SMCS332SpW User Manual

Interface between three spacewire links

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6.2

Data transfer via COMI

The transmission via the Communication Memory Interface (COMI) is a very efficient way to transfer data packets over the

SpaceWire-links. The CPU only fills the Communication Memory (DPRAM) with the relevant data words and sets the

registers in the SMCS332SpW that point on these words. Further transfer activities are applied by the SMCS332SpW

without any CPU intervention. For each link channel, 6 registers are provided. 4 registers to assign an area in the

Communication Memory and 2 registers which carry the current address value.

CHx_TX_SAR

CHx_TX_EAR

CHx_TX_CAR

CHx_RX_SAR

CHx_RX_EAR

CHx_RX_CAR

TX and RX registers are programmable independently thus there is no interference between TX and RX activities. With

writing on the End Address Register the transmit/receive activity of the respective channel is initiated. With reading the

Current Address Register the status of data transfer of this activity can be observed.

A successful packet transmission/reception or the occurrences of an error is indicated through an interrupt by the

SMCS332SpW. The cause of an interrupt can be read from the Interrupt Status Register (ISR) via the Host Control Interface

(HOCI).

The following events cause an interrupt and are important for the transmission via COMI in transparent mode:

SpaceWire link error (disconnect, parity, credit and ESC error)

packet transmission completed (TX Current Address Reg = TX End Address Reg.)

reception segment in Communication Memory full

packet reception completed (EOP or EEP received) (RX Current Address Reg. = RX End Address Reg.)

check sum error (if enabled)

With setting a bit in the Interrupt Mask Register the respective event is enabled.

The interrupt capability can be switched off by masking all interrupt sources through setting the complete interrupt mask

register to "0" when the system is not able to service it. In this case SMCS332SpW ISR can be polled to wait for the event.

The structure of storage of data words can be configured for each channel independently. The following list shows the

switches that are possible:

storage of one versus more packets per segment. If more than one packet is allowed to be stored in one

segment, the user must take care about the separation of the different packets.

data word width to 8 versus 16 versus 32

sign bit expand versus no expand in 8/16 bit mode

Furthermore the SMCS332SpW supports both little and big endian mode on its COMI (as well as for the HOCI) to be

compliant to the most processors.

Program Sequence

SMCS332SpW

User Manual

Function

Channel x Transmission Start Address Register

Channel x Transmission End Address Register

Channel x Transmission Current Address Register

Channel x Receive Start Address Register

Channel x Receive End Address Register

Channel x Receive Current Address Register

EADS Astrium GmbH, ASE2

Doc No: SMCS_ASTD_UM_100

Issue:

1.4

Updated: 9-Sep-2006

Page:

58 of 131

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