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Signal Name
Type Function
BOOTLINK
I
CMCS(1:0)*
O/Z Communication memory select lines. These pins are
CMRD*
O/Z Communication memory read strobe. This pin is asserted
CMWR*
O/Z Communication memory write strobe. This pin is asserted
CMADR(15:0)
O/Z Communication memory address. The SMCS outputs an
CMDATA(31:0)
IOZ Communication memory data. The SMCS inputs and
COCI
I
COCO
O
CAM
I
CPUR*
O
SES(3:0)*
O
LDI1
I
LSI1
I
LDO1
O
LSO1
O
LDI2
I
LSI2
I
LDO2
O
LSO2
O
LDI3
I
LSI3
I
LDO3
O
LSO3
O
TRST*
I
SMCS332SpW
User Manual
1:
host I/F Big Endian
0:
control by host
1:
control by link
asserted as chip selects for the corresponding banks of the
communication memory.
when the SMCS reads data from memory.
when the SMCS writes to data memory.
address on these pins.
outputs data from and to com. memory on these pins.
Communication interface 'occupied' input signal
Communication interface 'occupied' output signal
Communication interface arbitration master input signal
(see section 4.3)
1: master
0: slave
CPU Reset Signal (can be used as user defined flag)
Specific External Signals (can be used as user defined
flags)
Link Data Input channel 1
Link Strobe Input channel 1
Link Data Output channel 1
Link Strobe Output channel 1
Link Data Input channel 2
Link Strobe Input channel 2
Link Data Output channel 2
Link Strobe Output channel 2
Link Data Input channel 3
Link Strobe Input channel 3
Link Data Output channel 3
Link Strobe Output channel 3
Test Reset. Resets the test state machine.
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
65 of 131
max. output
load [pF]
current [mA]
6
25
6
25
6
25
6
25
3
25
3
50
3
50
3
50
12
25
12
25
12
25
12
25
12
25
12
25
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