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Eads Astrium SMCS332SpW User Manual

Interface between three spacewire links
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Summary of Contents for Eads Astrium SMCS332SpW

  • Page 2 Astrium GmbH. The contents are for confidential use only and are not to be disclosed to any others in any manner, in whole or in part, except with the express written approval of EADS Astrium GmbH or to the provision of the relevant contract.

  • Page 3: Table Of Contents

    Register address map............................18 4.1.1 SMCS332SpW status and control registers ....................18 4.1.2 SMCS332SpW channel 1 status and control registers ................19 4.1.3 SMCS332SpW channel 2 status and control registers ................20 4.1.4 SMCS332SpW channel 3 status and control registers ................21 4.1.5...
  • Page 4 Restrictions ............................... 49 Wormhole Routing ............................49 5.5.1 Overview..............................49 5.5.2 Wormhole routing on SMCS332SpW....................... 50 5.5.3 Routing Implementation on SMCS332SpW ..................... 50 5.5.4 SMCS332332SpW Routing Examples...................... 51 Header bytes generation ........................... 51 5.6.1 Header field control bit ..........................51 5.6.2 Routing and Checksum Generation......................
  • Page 5 Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 5 of 131 6.1.3 SMCS332SpW Interrupt Status Register (ISR) ..................56 6.1.4 SMCS332SpW Interrupt Mask Register ....................57 6.1.5 Channel specific configuration registers ....................57 6.1.5.1 SpaceWire Mode Register (CHx_DSM_MODR) ................. 57 6.1.5.2...
  • Page 6 Enable Command Execution Transaction ....................127 13.5.7 Critical Simple Command Execution Transaction .................. 128 13.6 Glossary................................129 14 Differences between the SMCS332SpW and the old SMCS332................ 130 14.1 Summary of changed/modified/added registers or register bits..............130 14.2 Pin Modifications............................131...

  • Page 7: Doc No: Smcs_Astd_Um_100

    Page: 7 of 131 1 Scope and Objectives This document describes in detail the new SMCS332SpW. The SMCS332SpW provides an interface between three SpaceWire links according to the SpaceWire Standard ECSS-E-50-12A and a data processing node like a CPU. List of applicable documents...

  • Page 8: List Of Abbreviations

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 8 of 131 List of Abbreviations Applicable Document Application Programming Interface ASIC Application Specific Integrated Circuit CODEC COder / DECoder COMI Communication Memory Interface Data Processing Unit...

  • Page 9: Introduction

    The SMCS332SpW provides an interface between 3 SpaceWire links according to the SpaceWire Standard ECSS-E-50-12A specification and a data processing node consisting of a CPU and a communication data memory. The SMCS332SpW provides HW supported execution of the major parts of the simple interprocessor communication protocol, particularly: ·...

  • Page 10: Interfaces

    CPU. A special pin is provided to select between control of the SMCS332SpW by HOCI or by link. If control by link is enabled, the host data bus functions as a 32-bit general purpose interface (GPIO).

  • Page 11: Operation Modes

    SMCS332SpW Control by SpaceWire link A feature of the SMCS332SpW is the possibility to control the SMCS332SpW not only via HOCI but via one of the three links. This allows to use the SMCS332SpW in systems without a local controller (µController, FPGA etc.). Since the HOCI is no longer used in this operation mode, it is instead available as a set of general purpose I/O (GPIO) lines.

  • Page 12: Ppu Functional Description

    Receive, Transmit, Acknowledge: the transmit and receive FIFOs decouple the SpaceWire link related operations from the SMCS332SpW related operations in all modes and such allows to keep the speed of the different units even when the source or sink of data is temporarily blocked.

  • Page 13: Application

    A/D-converter or sensor interfaces can be assembled with the SMCS332SpW because of the "control by link" feature. The complete control of the SMCS332SpW can be done via link from a central controller-node. The SMCS332SpW is a very high speed, scalable link-interface chip with fault tolerance features. The initial exploitation is for use in multi-processor systems where the standardization or the high speed of the links is an important issue and where reliability is a requirement.

  • Page 14: The Spacewire Link

    To compensate for these deficiencies of the SpaceWire specification, the SMCS332SpW implementations (the SMCS332SpW and the SMCS116SpW) introduce an (optional) transaction layer extension to the SpaceWire protocol standard. This high-level protocol extension supports applications in fault tolerant systems, heterogeneous architectures, feature power saving modes and remote configuration of the communication controller and autonomous command execution.

  • Page 15: Character Level Flow Control

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 15 of 131 Character Type Abbreviation Coding Data character P0DDDDDDDD control characters: Flow control P100 Normal End of Packet P101 Error End of Packet P110 Escape...

  • Page 16: Link Speeds

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 16 of 131 Link speeds The SpaceWire links can support a range of communication speeds, which are programmed by writing to registers. At reset all links are configured to run at the base speed of 10 Mbits/sec. Only the transmission speed of a link is programmed as reception is asynchronous.

  • Page 17: Spacewire State On Start Up

    SpaceWire link is started up it transmits NULL's. Data may not be transferred over the link until the receiving link has sent a FCT, which it will do as soon as it has been started. In remote mode (control by link) however, the SMCS332SpW will send characters as soon as it receives a NULL on one of the three links, the control link.

  • Page 18: Register Set

    4 Register Set This chapter describes the SMCS332SpW registers which can be read or written by the HOCI or via the link (in case the "control by link" is enabled) to control SMCS332SpW operations. All SMCS332SpW control operations are performed by writes or reads of the respective registers.

  • Page 19: Smcs332Spw Channel 1 Status And Control Registers

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 19 of 131 4.1.2 SMCS332SpW channel 1 status and control registers Port Width Register Function Reset Access Address (hex) Value (hex) CH1_DSM_MODR channel 1 DSM mode Register...

  • Page 20: Smcs332Spw Channel 2 Status And Control Registers

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 20 of 131 4.1.3 SMCS332SpW channel 2 status and control registers Port Width Register Function Reset Access Address (hex) Value (hex) CH2_DSM_MODR channel 2 DSM mode Register...

  • Page 21: Smcs332Spw Channel 3 Status And Control Registers

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 21 of 131 4.1.4 SMCS332SpW channel 3 status and control registers Port Width Register Function Reset Access Address (hex) Value (hex) CH3_DSM_MODR channel 3 DSM mode Register...

  • Page 22: Smcs332Spw Gpio Control Registers

    User Manual Updated: 9-Sep-2006 Page: 22 of 131 4.1.5 SMCS332SpW GPIO control registers These registers are only enabled when the SMCS332SpW is configured for "control by link" using the 'BOOTLINK' pin (see sections 2.3, 5.4 and 9.2). Port Width Register Function...

  • Page 23: Register Description

    Issue: User Manual Updated: 9-Sep-2006 Page: 23 of 131 Register Description 4.2.1 General SMCS Registers 4.2.1.1 SMCS332SpW Interface Control Register (SICR) - address: 0x00 - data width: 3 bit, D2:0 - access mode: read / write - reset value: 0x00...

  • Page 24: Route Control Status Register (Rt_Ctrl)

    Status channel 3 no connection connection to channel 1 connection to channel 2 connection to local fifo reserved SMCS332SpW Wormhole Route Enable Bit: Wormhole Routing disabled (Reset) Wormhole Routing enabled 4.2.1.4 Interrupt Status Register (ISR) - address: 0x04 – 0x07...
  • Page 25 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 25 of 131 Description channel 1: SpaceWire parity, disconnect, ESC or credit error. For more information refer to register CH1_DSM_STAR: channel SpaceWire status register channel 1: error For more information over this error flag refer to register CH1_ESR1 and CH1_EXR2 channel 1: data from the communication memory are read.
  • Page 26 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 26 of 131 address: 8 bit mode: 0x06 16 bit mode: 0x06 32 bit mode: 0x04 ISR Byte 2 Description channel 2: transmit fifo is empty (set after reset)

  • Page 27: Interrupt Mask Register (Imr)

    When COCI is asserted, the SMCS332SpW COMI interface completes the current access, places the interface in a high- impedance state and then deasserts the output signal COCO to indicate to the requesting SMCS332SpW that it is no longer driving the COMI bus.

  • Page 28: Prci Register (Prcir)

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 28 of 131 COMI_ACR values from 0x00 = disable communication memory interface 0x01 = is not allowed to 0x0F = max. CLK cycles between two accesses.

  • Page 29: Channel 1 Registers

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 29 of 131 4.2.2 Channel 1 Registers 4.2.2.1 Channel 1 SpaceWire Mode Register (CH1_DSM_MODR) - address: 0x10 - data width: 8 bit, D7:0 - access mode:...

  • Page 30: Eads Astrium Gmbh, Ase2

    (the link received to much normal characters or FCT control characters) always ‘0'/reserved Differences between the SMCS332 and the SMCS332SpW for the bits D0, D3 and D4: When D0, D3 and D4 are set, the SpaceWire link is/was in the "Run" state. See [AD1].

  • Page 31: Channel 1 Spacewire Test Register (Ch1_Dsm_Tstr)

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 31 of 131 4.2.2.4 Channel 1 SpaceWire Test Register (CH1_DSM_TSTR) - address: 0x13 - data width: 4 bit, D3:0 - access mode: read / write - reset value: The test register is writeable only when bit 7 of register CH1_DSM_MODR is set.

  • Page 32: Channel 1 Route Address Register (Ch1_Rt_Addr)

    SpaceWire cells. The result of the comparison is used to determine the destination of the packet. It can be delivered to the internal channel FIFO or to one of the two other SpaceWire channels inside the SMCS332SpW. For more information see chapter 5.5 Description register content will be compared with first byte of an incoming packet (if routing is enabled) 4.2.2.7...

  • Page 33: Channel 1 Control Register 1 (Ch1_Cntrl1)

    See Note. header field control bit when set, the SMCS332SpW use the first byte of a packet as number of bytes which are transmitted as header bytes. If checksum enabled, this bytes are excluded from the checksum. The range for the header field is from minimum 2bytes (number byte + header byte) to maximum16 bytes.

  • Page 34: Channel 1 Control Register 2 (Ch1_Cntrl2)

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 34 of 131 DATA Figure Checksum generation Example: the packet consists of 259 * 0xFF: 1. checksum = 0x00000 + 0xFF + 0 = 0x000FF 2. checksum = 0x000FF + 0xFF + 0 = 0x001FE …...

  • Page 35: Channel 1 Header Transaction Id (Ch1_Htid)

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 35 of 131 4.2.2.10 Channel 1 Header Transaction ID (CH1_HTID) - address: 0x1A - data width: 8 bit, D7:0 - access mode: read only - reset value: 0x00 When protocol mode enabled.

  • Page 36: Channel 1 Error Source Register 2 (Ch1_Esr2)

    The channel 1 error source register 2 is readable and the bits are reset only by writing '1', thus ensuring status never gets missed by software. Description Simple Interprocessor Command (SIC) sequence error. That means: the SMCS332SpW received an unexpected acknowledge packet. Received SIC packet with a wrong checksum (only, when generate checksum enabled, bit 4 of register CH1_CNTRL1).

  • Page 37: Channel 1 Transmit Start Address Register (Ch1_Tx_Sar)

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 37 of 131 Description transmit data port width the COMI data port operates in transmit direction with 8 bit (after reset), each access of the COMI...

  • Page 38: Channel 1 Transmit End Address Register (Ch1_Tx_Ear)

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 38 of 131 - reset value: 0x0000 The value of CH1_TX_SAR shows the start address, the value of CH1_TX_EAR shows the end address of a packet in the communication memory, which should be transmitted over channel 1.

  • Page 39: Channel 1 Transmit Fifo (Ch1_Tx_Fifo)

    For data transfer over the transmit FIFO, the host processor has to send the EOP character at the end of the packet. If the host processor sets bit 0 or 1 or both, the SMCS332SpW sends an EOP character at the end of the packet.

  • Page 40: Channel 1 Receive End Address Register (Ch1_Rx_Ear)

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 40 of 131 Description lower byte of the start address Byte 1 at address 0x29: (only in 8 bit mode of the HOCI data port): Description upper byte of the start address 4.2.2.21...

  • Page 41: Channel 1 Receive Fifo (Ch1_Rx_Fifo)

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 41 of 131 Byte 1 at address 0x2D: (only in 8 bit mode of the HOCI data port): Description upper byte of the current address 4.2.2.23...

  • Page 42: Time Code Registers

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 42 of 131 4.2.5 Time Code Registers 4.2.5.1 Time Code Control Register (TIME_CNTRL) - address: 0x78 - data width: 8 bit, D7:0 - access mode: D4:0: read / write...
  • Page 43 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 43 of 131 Description After a write access to this register, the new value will be send as a time code character over the active SpaceWire links.

  • Page 44: Smcs332Spw Modes

    - register byte 3 is connected with pin HDATA7 - HDATA0 The registers of the SMCS332SpW are 1, 2 or 4 Bytes wide. That means, if the HOCI data port is in 8 bit mode, 4 read or write accesses are necessary to access a 4 Byte register (e. g. the interrupt mask register). In 16/32 bit mode the data bits 31 - 8 are '0' if an 8 bit register is read.

  • Page 45: Comi Data Transfer

    - byte 2 is transferred via CMDATA15 - CMDATA8 - byte 3 is transferred via CMDATA7 - CMDATA0 COMI Arbitration The operation of two SMCS332SpW in master / slave mode is shown below: – All Rights Reserved – Copyright per DIN 34 –...
  • Page 46 Now, SMCS332SpW -B "parks" on the bus until there is a request from SMCS332SpW -A. If a bus owner releases the bus after a request from the other SMCS332SpW, it has to wait for N-1 Cycles (N = value from Register COMI_ACR), before it can request the bus again.
  • Page 47 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 47 of 131 (4-1) = 3 readcycles 25 MHz * 3/12 * 4 Bytes/cycle = 25 Mbyte/s Note: COMI_ACR value 0x01 is not allowed. COMI_ACR value 0x00 means: disable communication memory interface.

  • Page 48: Control By Link

    Determination of the control link After the reset signal is released the SMCS332SpW will wait for NULL characters on the three links. It will not start a link until it has received NULL characters on this link. Only then the SMCS332SpW will send NULL characters itself. After the links are active, the SMCS332SpW scans these links for data (characters).

  • Page 49: Host Data Bus / Gpio Port

    The block diagram below shows a typical constellation of a remotely controlled SMCS332SpW controlled via link 2 from another SpaceWire device (in this case an SMCS332SpW). Note that if data is to be written to the RAM of the remote- controlled SMCS332SpW, an extra link (in the figure below this is link 1) needs to be used.

  • Page 50: Wormhole Routing On Smcs332Spw

    The SMCS332SpW interprets the signals on its inputs as sequences of packets. It takes the first byte of data as the header of the packet, which determines what it will do with the whole packet. The length and contents of the remainder of the packet are arbitrary.

  • Page 51: Smcs332332Spw Routing Examples

    CHx_CNTRL1. Description: If bit 5 in the register CHx_CNTRL1 is set, the SMCS332SpW will use the first byte of an incoming data to be transmitted (from COMI or HOCI) as number of bytes which are excluded from checksum (if checksum is enabled). The allowed range is from 1 to 15.
  • Page 52 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 52 of 131 This means that data has to start at the next modulo 4 bytes. The rest of a 4-byte-block which is not covered by the number of header bytes will not be transmitted.

  • Page 53: Routing And Checksum Generation

    In this case the SMCS332SpW, generates two checksum bytes from the data bytes and appends these bytes at the end of the data bytes. The SMCS332SpW at the other end of the virtual link generates again a checksum from the received bytes( without the last 2 bytes) and compares these with the received checksum (last 2 bytes).

  • Page 54: Time Code Interface

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 54 of 131 Time Code Interface Both time code interface registers TIME_CNTRL and TIME_CODE controls the receiving and transmitting of time code characters. A time code on the SpaceWire links consists of an ESC control character and a data character: the time code value.

  • Page 55: Smcs332Spw Receive Time Code

    SMCS332SpW receive time code Status bits 5, 6 or 7 in register TIME_CNTRL will be set, when the SMCS332SpW receives a time code character over link1, 2 or 3. If bit 2 of the TIME_CNTRL register is set, the received time code will be written in the TIME_CODE register.

  • Page 56: Programming And Operation Modes

    SMCS332SpW Initialization After power-up or any other reset the configuration registers of the SMCS332SpW are set to their default values (see chapter register description). For proper operation, each application has to adapt them according to their specific needs.

  • Page 57: Smcs332Spw Interrupt Mask Register

    Communication Memory (refer to chapter "Data Transfer via COMI"). 6.1.5.3 Control Register 1 (CHx_CNTRL1) No configuration has to be made if transmission in transparent mode is desired. For operation with the SMCS332SpW in protocol mode the respective bits are to set, see chapter 13. 6.1.5.4 SpaceWire Command Register (CHx_DSM_CMDR) The link can be started by writing a '1' to bit 1 of this register.

  • Page 58: Data Transfer Via Comi

    The interrupt capability can be switched off by masking all interrupt sources through setting the complete interrupt mask register to “0" when the system is not able to service it. In this case SMCS332SpW ISR can be polled to wait for the event.
  • Page 59 RX-address generation after receiving an EOP/EEP and for the reception of another packet the receive channel must be set up again. In the second case the packets are appended and the SMCS332SpW only signals that the end of the segment is reached (RX generator finished).
  • Page 60 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 60 of 131 * <CH2 RX generator finished> smcs_reg_write(SMCS, SMCS_IMR0, 0x2014); /* select transmit rate to max. Transmit bitrate*/ smcs_reg_write(SMCS, CH1_DSM_MODR, 0x08); smcs_reg_write(SMCS, CH2_DSM_MODR, 0x08); /* start the links */ smcs_reg_write(SMCS, CH1_DSM_CMDR, 0x02);...

  • Page 61: Data Transfer Via Hoci

    Communication Memory. Also applications with sample oriented processing can take advantage of this feature. The CPU user makes usage of its direct access on the SMCS332SpW internal FIFOs to read/write the single data words to be transferred. With checking the FIFO flags the CPU must assure to handle the process of communication properly. This action results in a programming overhead of course, but saves board space and power.

  • Page 62: Special Behaviour In Case Of Spacewire Link Error

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 62 of 131 Example #2: The following two C-code routines show a handling of transferring small packets. (m: SMCS number, n: channel number) #define TXfull 0x02;...
  • Page 63 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 63 of 131 causes a special behaviour if a link error occurs. The remainder of the last written packet remains in the internal pipe which is not cleared in case of a SpaceWire link error. After the link reconnects, this remainder will be transmitted immediately after a new data character or an EOP is written to the HOCI FIFO.

  • Page 64: Signal Description

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 64 of 131 7 Signal Description The Figure below shows the SMCS332SpW embedded in a typical module environment: SMCS332SpW Processor HOSTBIGE HINTR INTERRUPT IN BOOTLINK HSEL CHIP SELECTS...
  • Page 65 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 65 of 131 Signal Name Type Function max. output load [pF] current [mA] host I/F Big Endian BOOTLINK control by host control by link CMCS(1:0)* O/Z Communication memory select lines. These pins are asserted as chip selects for the corresponding banks of the communication memory.
  • Page 66 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 66 of 131 Signal Name Type Function max. output load [pF] current [mA] Test Clock. Provides an asynchronous clock for JTAG boundary scan. Test Mode Select. Used to control the test state machine.

  • Page 67: Electrical Specifications

    = GND see also the signal description in chapter 7. Although specified for TTL outputs, all SMCS332SpW outputs are CMOS compatible and will drive to VCC and GND assuming no dc loads. – All Rights Reserved – Copyright per DIN 34 –...

  • Page 68: Power Consumption

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 68 of 131 Power consumption Max. power consumption figures at V = + 5.5V/ -55°C, CLK = 25MHz are: Operation Mode Power consumption [mA] not clocked...

  • Page 69: Pll Filter

    SMCS332SpW provides separate supply pins for its internal logic and for its external drivers. All GND pins should have a low impedance path to ground. A ground plane is required in SMCS332SpW systems to reduce this impedance, minimizing noise.

  • Page 70: Timing Parameters

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 70 of 131 9 Timing Parameters Clock Signals = 5 V ± 0.5V Description Symbol Min. Max. CLK period CLK width high CLKH CLK width low CLKL Max.
  • Page 71 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 71 of 131 = 5 V ± 0.5V Description Symbol Min. Max. CLK10 period CLK10 CLK10 width high CLK10H CLK10 width low CLK10L Typically 10 MHz = 3.3 V ±...

  • Page 72: Reset

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 72 of 131 Reset = 5 V ± 0.5V Description Symbol Min. Max. Unit RESET* low pulse width 2 * t RSTW Output disable after RESET* low...

  • Page 73: Host Read

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 73 of 131 Host Read = 5 V ± 0.5V Description Symbol Min. Max. Unit HSEL*, HRD* and SMCSADR and HADR setup before CLK high HRSU...
  • Page 74 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 74 of 131 = 3.3 V ± 0.3V Description Symbol Min. Max. Unit HSEL*, HRD* and SMCSADR and HADR setup before CLK high HRSU HADR, SMCSADR hold after HSEL*, HRD* high...

  • Page 75: Host Write

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 75 of 131 Host Write = 5 V ± 0.5V Description Symb. Min. Max. Unit HSEL*, HWR* and SMCSADR and HADR setup before CLK high HWSU...
  • Page 76 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 76 of 131 Description Symb. Min. Max. Unit HSEL*, HWR* and SMCSADR and HADR setup before CLK high HWSU HADR, SMCSADR hold after HSEL* or HWR* high...

  • Page 77: Comi Read

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 77 of 131 COMI Read = 5 V ± 0.5V Description Symbol Min. Max. Unit CMCS0*, CMCS1* and CMRD* low and CMADR valid after CLK CRCA...

  • Page 78: Comi Write

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 78 of 131 COMI Write = 5 V ± 0.5V Description Symbol Min. Max. Unit CMCS0*, CMCS1* and CMWR* low and CMADR valid after CLK CWCA...

  • Page 79: Comi Arbitration

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 79 of 131 COMI Arbitration = 5 V ± 0.5V Description Symbol Min. Max. Unit COM Interface disable after CLK low CAID COM Interface enable after CLK high...

  • Page 80: Cpur, Ses, Interrupt

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 80 of 131 CPUR, SES, Interrupt = 5 V ± 0.5V Description Symbol Min. Max. Unit CPUR*, SESx*, HINTR* delay after CLK high OUTC = 3.3 V ± 0.3V...

  • Page 81: Links

    LDSI Note: is the minimum separation time between consecutive edges on the data and strobe inputs that the LDSI SMCS332SpW can discriminate correctly (for all speeds from 1.25 Mbps - 200 Mbps). = 3.3 V ± 0.3V Description Symbol Min.

  • Page 82: Test Port (Jtag)

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 82 of 131 9.10 Test Port (JTAG) = 5 V ± 0.5V Description Symbol Min. Max. TCK period TCK width high TCKH TCK width low TCKL...
  • Page 83 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 83 of 131 Description Symbol Min. Max. TRST* pulse width 2 * t TRST SMCS Inputs setup before TCK high SYSS SMCS Inputs hold after TCK high...

  • Page 84: Mechanical Data

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 84 of 131 10 Mechanical Data 10.1 Package Dimensions 196-Pin Ceramic Quad Flat Pack (MQFP) SYMBOL MILLIMETERS INCHES 2.36 2.97 0.093 0.117 0.2 typ 0.008 typ D, E 38.74...

  • Page 85: Pin Assignment

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 85 of 131 10.2 Pin Assignment The table below lists the pins of the SMCS332SpW Name Pin Number Name Pin Number Name Number PLLOUT HDATA18 CMDATA8...
  • Page 86 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 86 of 131 Name Pin Number Name Pin Number Name Number SMCSADR0 CMRD* CMDATA30 SMCSADR1 CMWR* CMDATA31 SMCSADR2 CMADR0 SMCSADR3 CMADR1 SMCSID0 CMADR2 VCC_3VOLT SMCSID1 CMADR3...

  • Page 87: Additional Informations

    Yes; the SMCS332SpW features CMOS outputs and TTL inputs. When the SMCS332SpW is connected to a dual port memory, can it monitor the “busy” wire of the DPRAM? No. External logic is required for that. Due to the mechanism applied in the SMCS, it is not necessary to monitor busy wire when data is flowing via COMI.
  • Page 88 88 of 131 SMCS332SpW protocol specification (see Appendix B). When using the SMCS332SpW internal link loopback test mechanism, do the link signals propagate outside the SMCS332SpW? Yes, but you can avoid this by using the CHx_DSM_TSTR register bit 4: link output mute.
  • Page 89 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 89 of 131 and Byte3 Bit 7='0' COMI data port is set to 8 Bit width: datalines: 31-24 23-16 15-8 Byte0 if CHx_COMICFG bit 7 = 0...

  • Page 90: Bsdl File For The Smcs332Spw

    Page: 90 of 131 11.2 BSDL File for the SMCS332SpW Below is the BSDL file required for using the JTAG port of the SMCS332SpW. -- BSDL for SMCS332SpW -- Uses HP's BSDL format and compiles correctly using HP's -- parser or compiler of JTAG Technologies...
  • Page 91 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 91 of 131 TDO : out bit; TMS : in bit; TRST : in bit; CMADR : out bit_vector(0 to 15); CMCS0 : out bit; CMCS1 : out bit;...
  • Page 92 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 92 of 131 "LSI2:181," & "LSI3:189," & "RESET:5," & "SMCSADR0:33," & "SMCSADR1:34," & "SMCSADR2:35," & "SMCSADR3:36," & "SMCSID0:37," & "SMCSID1:38," & "SMCSID2:39," & "SMCSID3:40," & "TIME_CODE_SYNC:192," &...
  • Page 93 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 93 of 131 attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true;...
  • Page 94 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 94 of 131 " 227 (BC_1, TIME_C_SY, input, X)," & " 226 (BC_1, LSO3, output2, X)," & -- output2 for internal tristate? " 225 (BC_1, LDO3, output2, X),"...
  • Page 95 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 95 of 131 " 178 (BC_1, CMDATA(15), input, X)," & " 177 (BC_1, CMDATA(14), output3, X, 212, 0, Z)," & " 176 (BC_1, CMDATA(14), input, X)," &...
  • Page 96 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 96 of 131 " 129 (BC_1, CMRD, output2, X)," & " 128 (BC_1, CMCS1, output2, X)," & " 127 (BC_1, CMCS0, output2, X)," & " 126 (BC_1, COCO, output2, X),"...
  • Page 97 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 97 of 131 " 80 (BC_1, HDATA(19), input, X)," & " 79 (BC_1, * control, 0)," & -- HOCI Data Output Enable " 78 (BC_1, HDATA(18), output3, X, 79, Z),"...
  • Page 98 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 98 of 131 " 31 (BC_1, * control, 0)," & -- HOCI Data Output Enable " 30 (BC_1, HDATA(2), output3, X, 31, Z)," & " 29 (BC_1, HDATA(2), input, X),"...
  • Page 99 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 99 of 131 *********************************** "32" "BOOTLINK" "168" "BYPPLL" "92" "CAM" "4" "CLK" "6" "CLK10" "93" "COCI" "22" "HADR0" "23" "HADR1" "24" "HADR2" "25" "HADR3" "26" "HADR4"...

  • Page 100: Issue: 1.4

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 100 of 131 "111" "CMADR8" OUTZ "112" "CMADR9" OUTZ "113" "CMADR10" OUTZ "114" "CMADR11" OUTZ "117" "CMADR12" OUTZ "118" "CMADR13" OUTZ "119" "CMADR14" OUTZ "120" "CMADR15"...

  • Page 101: Issue: 1.4

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 101 of 131 "153" "CMDATA22" "154" "CMDATA23" "157" "CMDATA24" "158" "CMDATA25" "159" "CMDATA26" "162" "CMDATA27" "163" "CMDATA28" "164" "CMDATA29" "165" "CMDATA30" "166" "CMDATA31" "43" "HDATA0" "44"...

  • Page 102: Issue: 1.4

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 102 of 131 "66" "GND7" "74" "GND8" "79" "GND9" "84" "GND10" "98" "GND11" "107" "GND12" "116" "GND13" "125" "GND14" "130" "GND15" "135" "GND16" "143" "GND17" "151" "GND18"...

  • Page 103: Issue: 1.4

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 103 of 131 "175" "NC1" "182" "NC2" *********************************** END PIN_LIST INSTRUCTION_REGISTER instr PURPOSE : "select register and BST mode" LENGTH CAPTURE : "101" INSTRUCTION_LIST ****************************************************** * INSTR...

  • Page 104: Issue: 1.4

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 104 of 131 BYPASS_REGISTER BYPASS PURPOSE : "short cut" LENGTH CAPTURE : "0" END BYPASS_REGISTER BOUNDARY_SCAN_REGISTER BOUNSCAN PURPOSE : "scan line along boundary" LENGTH : 233...
  • Page 105 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 105 of 131 BC_1_INPUT "CMDATA27" "162" BC_1_INPUT "CMDATA26" "159" BC_1_INPUT "CMDATA26" "159" BC_1_INPUT "CMDATA25" "158" BC_1_INPUT "CMDATA25" "158" BC_1_INPUT "CMDATA24" "157" BC_1_INPUT "CMDATA24" "157" BC_1_INPUT "CMDATA23"...
  • Page 106 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 106 of 131 BC_1_INPUT "CMDATA2" "123" BC_1_INPUT "CMDATA2" "123" BC_1_INPUT "CMDATA1" "122" BC_1_INPUT "CMDATA1" "122" BC_1_INPUT "CMDATA0" "121" BC_1_INPUT "CMDATA0" "121" BC_1_INPUT "-" BC_1_INPUT "CMADR15" "120"...
  • Page 107 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 107 of 131 BC_1_INPUT "HDATA27" "80" BC_1_INPUT "-" BC_1_INPUT "HDATA26" "77" BC_1_INPUT "HDATA26" "77" BC_1_INPUT "-" BC_1_INPUT "HDATA25" "76" BC_1_INPUT "HDATA25" "76" BC_1_INPUT "-" BC_1_INPUT "HDATA24"...
  • Page 108 EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 108 of 131 BC_1_INPUT "-" BC_1_INPUT "HDATA10" "55" BC_1_INPUT "HDATA10" "55" BC_1_INPUT "-" BC_1_INPUT "HDATA9" "54" BC_1_INPUT "HDATA9" "54" BC_1_INPUT "-" BC_1_INPUT "HDATA8" "53" BC_1_INPUT "HDATA8"...

  • Page 109: Issue: 1.4

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 109 of 131 BC_1_INPUT "HADR0" "22" BC_1_INPUT "HINTR" "19" BC_1_INPUT "-" BC_1_INPUT "HACK" "18" BC_1_INPUT "HWR" "17" BC_1_INPUT "HRD" "16" BC_1_INPUT "HSEL" "15" ******************************************************************************* END CHAIN_LIST...

  • Page 110: Handling Empty Packets

    Due to an anomaly in the SpaceWire CODEC (Coder / Decoder) version 1.4, which is used in the SMCS332SpW, the SMCS332SpW behavior is affected when more than one empty packet is received in a row. In this case the credit count is not updated correctly.

  • Page 111: Issue: 1.4

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 111 of 131 *after Link-Initialisation/Disconnect the RCVEOP (received EOP) flag is cleared, therefore an EOP/EEP transmitted directly after link connects is counted properly and can be read from Rx-Buffer...

  • Page 112: Issue: 1.4

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 112 of 131 1 EOP 1 EOP 1 FCT 1 EOP Empty packet 7 Data Bytes 7 Byte 1 EOP 1 EOP 1 FCT 1 EOP...

  • Page 113: Workaround

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 113 of 131 12.2 Workaround A stop at either end of the link causes a disconnect and hence clears this problem. Note that there is NO need to reset the entire device Please do make sure that this situation be treated properly if consecutive empty packets are expected.

  • Page 114: Simple Interprocessor Communication Protocol Specification

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 114 of 131 13 Simple Interprocessor Communication Protocol Specification 13.1 Application Scenario The purpose of this protocol specification is to provide a framework which allows the exchange of data and simple system control commands between single nodes of a multiprocessor system.

  • Page 115: Assumptions About The Environment

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 115 of 131 13.2 Assumptions about the Environment The protocol specified here is intended to work on top of the SpaceWire link protocol. This covers e.g. link startup, low level error handling, low level flow control, timeouts, routing provisions and the like.

  • Page 116: Execution Of Control Commands

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 116 of 131 node CPU's working memory. If required, it is up to higher levels of a communication protocol to provide this acknowledge. Refer to para. 4.1 for details.

  • Page 117: Complex Control Commands

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 117 of 131 Reset Link Interface Unit HW This command performs a hard reset (interrupting all currently running transmissions) of all link interfaces integrated within one link interface unit.

  • Page 118: Procedure Rules

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 118 of 131 This command is required since the link end which intents to stop link operation must inform the other end of the link. Otherwise the link shutdown might be interpreted as a link failure.

  • Page 119: Access To Command Signal Output Ports

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 119 of 131 Complex Commands Issuing complex commands results in two acknowledges: the low level acknowledge of the successful reception of the data packet containing the complex command and a high level acknowledge (contained in a response data packet) with information on e.g.

  • Page 120: Reset Commands

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 120 of 131 After a critical simple command has been executed, the simple command execution state is immediately changed from 'enable' to 'disable'. This assures that every critical simple command execution must be preceded by a 'enable' command.

  • Page 121: Shutdown Link Channel Operation / Restart Link Channel Operation

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 121 of 131 received and decoded correctly. Data received previous to the reset command is still forwarded to the node's working memory. Utilizing the interrupt signal indicating to the node CPU that an externally commanded link reset has occurred, the CPU can then decide on invalidating data already received via this channel.

  • Page 122: Encoding (Format) Of Transactions

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 122 of 131 13.5 Encoding (Format) of Transactions 13.5.1 Header and EOP Coding DEST Destination address of the packet 8 bit field CNTRL 8 bit control word for commands and acknowledges according to para.

  • Page 123: Issue: 1.4

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 123 of 131 Req. Command Specification Remarks Spec reserved for future use, Bit 3-0 are not interpreted Complex Command Request (coded within the datafield), Bit 2-0 are not interpreted...

  • Page 124: Link Interface Status Register Encoding

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 124 of 131 13.5.3 Link Interface Status Register Encoding General Layout of the Link Interface Status Register: Bit 3 - Bit 0 (LSB) Link Interface Operation Mode...

  • Page 125: Data Transfer Type Transactions

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 125 of 131 13.5.4 Data Transfer Type Transactions Requester Packet DEST CNTRL DATA CNTRL = Transfer Data, Complex Command Request or Complex Command Acknowledge DATA =...

  • Page 126: Read Link Interface Status Register Transaction

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 126 of 131 13.5.5 Read Link Interface Status Register Transaction Requester Packet DEST CNTRL CNTRL = Read Link Interface Status Register Actions: Reads the Link Interface Status Register...

  • Page 127: Enable Command Execution Transaction

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 127 of 131 13.5.6 Enable Command Execution Transaction Requester Packet DEST CNTRL CNTRL = Enable Safety Critical Command Actions: Enable the execution of a following safety critical command...

  • Page 128: Critical Simple Command Execution Transaction

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 128 of 131 13.5.7 Critical Simple Command Execution Transaction Requester Packet DEST CNTRL CNTRL = Simple Command Request (refer to para 5.2) Actions: Execute the requested simple command...

  • Page 129: Glossary

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 129 of 131 13.6 Glossary Communication Memory Part of a node's working memory reserved for communication. Computing Node A node which performs only computing tasks. Controlling Node A node which is allowed to perform system control tasks.

  • Page 130: Differences Between The Smcs332Spw And The Old Smcs332

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 130 of 131 14 Differences between the SMCS332SpW and the old SMCS332 Summary of changed/modified/added registers or register bits 14.1 Address Register Description SMCS332 Description SMCS332SpW 0x04...

  • Page 131: Pin Modifications

    EADS Astrium GmbH, ASE2 SMCS332SpW Doc No: SMCS_ASTD_UM_100 Issue: User Manual Updated: 9-Sep-2006 Page: 131 of 131 Address Register Description SMCS332 Description SMCS332SpW the end of the packet '1' = send NO EOP token at the end of the packet...

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