Table of Contents
Advertisement
4.2.2.3
Channel 1 Link SpaceWire Status Register (CH1_DSM_STAR)......................................................... 30
4.2.2.4
Channel 1 SpaceWire Test Register (CH1_DSM_TSTR) .................................................................... 31
4.2.2.5
Channel 1 Address Register (CH1_ADDR).......................................................................................... 31
4.2.2.6
Channel 1 Route Address Register (CH1_RT_ADDR) ........................................................................ 32
4.2.2.7
Channel 1 Protocol Status Register (CH1_PR_STAR)......................................................................... 32
4.2.2.8
Channel 1 Control Register 1 (CH1_CNTRL1).................................................................................... 33
4.2.2.9
Channel 1 Control Register 2 (CH1_CNTRL2).................................................................................... 34
4.2.2.10
Channel 1 Header Transaction ID (CH1_HTID) .............................................................................. 35
4.2.2.11
Channel 1 Header Control Byte (CH1_HCNTRL) ........................................................................... 35
4.2.2.12
Channel 1 Error Source Register 1 (CH1_ESR1) ............................................................................. 35
4.2.2.13
Channel 1 Error Source Register 2 (CH1_ESR2) ............................................................................. 36
4.2.2.14
Channel 1 COMI Configuration Register (CH1_COMICFG) .......................................................... 36
4.2.2.15
Channel 1 Transmit Start Address Register (CH1_TX_SAR) .......................................................... 37
4.2.2.16
Channel 1 Transmit End Address Register (CH1_TX_EAR) ........................................................... 38
4.2.2.17
Channel 1 Transmit Current Address Register (CH1_TX_CAR) ..................................................... 38
4.2.2.18
Channel 1 Transmit FIFO (CH1_TX_FIFO) .................................................................................... 39
4.2.2.19
Channel 1 Transmit EOP Bit Register (CH1_TX_EOPB) ................................................................ 39
4.2.2.20
Channel 1 Receive Start Address Register (CH1_RX_SAR) ........................................................... 39
4.2.2.21
Channel 1 Receive End Address Register (CH1_RX_EAR) ............................................................ 40
4.2.2.22
Channel 1 Receive Current Address Register (CH1_RX_CAR) ...................................................... 40
4.2.2.23
Channel 1 Receive FIFO (CH1_RX_FIFO)...................................................................................... 41
4.2.2.24
Channel 1 Status Register (CH1_STAR) .......................................................................................... 41
4.2.3
Channel 2 Registers .................................................................................................................................. 41
4.2.4
Channel 3 Registers .................................................................................................................................. 41
4.2.5
Time Code Registers................................................................................................................................. 42
4.2.5.1
Time Code Control Register (TIME_CNTRL) ..................................................................................... 42
4.2.5.2
Time Code Value Register (TIME_CODE) .......................................................................................... 42
5
SMCS332SpW Modes............................................................................................................................................. 44
5.1
HOCI Data Transfer ......................................................................................................................................... 44
5.2
COMI Data Transfer ........................................................................................................................................ 45
5.3
COMI Arbitration ............................................................................................................................................. 45
5.4
Control by Link ................................................................................................................................................. 48
5.4.1
Selecting remote mode.............................................................................................................................. 48
5.4.2
Determination of the control link .............................................................................................................. 48
5.4.3
Protocol and Commands ........................................................................................................................... 48
5.4.4
Host Data Bus / GPIO Port ....................................................................................................................... 49
5.4.5
Restrictions ............................................................................................................................................... 49
5.5
Wormhole Routing ............................................................................................................................................ 49
5.5.1
Overview................................................................................................................................................... 49
5.5.2
Wormhole routing on SMCS332SpW....................................................................................................... 50
5.5.3
Routing Implementation on SMCS332SpW ............................................................................................. 50
5.5.4
SMCS332332SpW Routing Examples...................................................................................................... 51
5.6
Header bytes generation ................................................................................................................................... 51
5.6.1
Header field control bit ............................................................................................................................. 51
5.6.2
Routing and Checksum Generation........................................................................................................... 53
5.7
Time Code Interface.......................................................................................................................................... 54
5.7.1
SMCS33SpW transmit time code ............................................................................................................. 54
5.7.2
SMCS332SpW receive time code ............................................................................................................. 55
5.8
SMCS332SpW Version Control ........................................................................................................................ 55
6
Programming and Operation Modes .................................................................................................................... 56
6.1
SMCS332SpW Initialization.............................................................................................................................. 56
6.1.1
SMCS332SpW Interface Control Register ............................................................................................... 56
6.1.2
Transmit Bitrate Register (TRS_CTRL) ................................................................................................... 56
- All Rights Reserved - Copyright per DIN 34 -
1.4
Page:
4 of 131
Advertisement
Table of Contents
