Data Transfer Via Hoci - Eads Astrium SMCS332SpW User Manual

Interface between three spacewire links

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6.3

Data Transfer via HOCI

The Host Control Interface is mainly designed for the access to internal SMCS332SpW registers. But for small packets data

transfer can be performed via this interface for the purpose of saving board space and power through the absence of the

Communication Memory. Also applications with sample oriented processing can take advantage of this feature.

The CPU user makes usage of its direct access on the SMCS332SpW internal FIFOs to read/write the single data words to be

transferred. With checking the FIFO flags the CPU must assure to handle the process of communication properly. This action

results in a programming overhead of course, but saves board space and power.

Program Sequence

The transfer is controlled by 4 registers:

CHx_TX_FIFO

CHx_TX_EOPB

CHx_RX_FIFO

CHx_STAR

For transmitting data the CPU writes the words directly to the channel transmit FIFO address. The end of a transmit packet is

indicated by writing on the EOP-Bit- register. The EOP termination is appended to the last word as a control character on the

link. To recognize the end of an incoming (receiving) packet the CPU reads the channel status or the interrupt status register.

(Note: Reading the interrupt status register will clear its contents. Thus relevant information concerning other link channels

must be saved for further evaluation if so required.)

Before accessing the FIFOs, the CPU must evaluate the status of the FIFO flags. For each channel, FIFO status flags are

provided:

transmit FIFO empty

transmit FIFO full

receive FIFO not empty

receive FIFO full

With the first write access on the transmit FIFO the 'transmit FIFO empty'-flag becomes inactive. The 'transmit FIFO full'

flag must be examined carefully to assure that no data words will be overwritten.

The first two data words once written in the transmit FIFO are not immediately sent towards the listening node but remain in

the queue. Either with adding the next word to the packet or writing the EOP bit on the Transmit EOP Bit Register the

SMCS332SpW begins transmission of one word or the whole packet respectively.

SMCS332SpW

User Manual

Function

channel x Transmit FIFO

channel x Transmit EOP Bit Register

channel x Receive FIFO

channel x Status Register

EADS Astrium GmbH, ASE2

Doc No: SMCS_ASTD_UM_100

Issue:

1.4

Updated: 9-Sep-2006

Page:

61 of 131

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