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* <CH2 RX generator finished>
*/
smcs_reg_write(SMCS, SMCS_IMR0, 0x2014);
/* select transmit rate to max. Transmit bitrate*/
smcs_reg_write(SMCS, CH1_DSM_MODR, 0x08);
smcs_reg_write(SMCS, CH2_DSM_MODR, 0x08);
/* start the links */
smcs_reg_write(SMCS, CH1_DSM_CMDR, 0x02);
smcs_reg_write(SMCS, CH2_DSM_CMDR, 0x02);
/* start transfers */
smcs_reg_write(SMCS, CH1_TX_SAR, 0x00);
smcs_reg_write(SMCS, CH1_TX_EAR, 0x0F);
smcs_reg_write(SMCS, CH1_RX_SAR, 0x100);
smcs_reg_write(SMCS, CH1_RX_EAR, 0x13F);
smcs_reg_write(SMCS, CH2_RX_SAR, 0x200);
smcs_reg_write(SMCS, CH2_RX_EAR, 0x2FF);
while (1)
{
static int tx1_count = 0;
wait_for_int();
if (ch1_tx_int_occured && (tx1_count == 0))
{
ch1_tx_int_occured = 0;
tx1_count++;
/* start transfer of second packet over Link #1 */
smcs_reg_write(SMCS, CH1_TX_SAR, 0x10);
smcs_reg_write(SMCS, CH1_TX_EAR, 0x1F);
}
if (ch1_tx_int_occured && ch1_rx_int_occured && ch2_rx_int_occured)
break;
}
SMCS332SpW
User Manual
– All Rights Reserved – Copyright per DIN 34 –
/* wait for interrupts */
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
60 of 131
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