Channel 1 Control Register 2 (Ch1_Cntrl2); All Rights Reserved – Copyright Per Din - Eads Astrium SMCS332SpW User Manual

Example: the packet consists of 259 * 0xFF:
1. checksum
2. checksum
...
256. checksum
257. checksum
258. checksum
259. checksum
1. checksum byte send over SpaceWire = checksum[7:0]
2. checksum byte send over SpaceWire = checksum[15:8]
See also register CHx_ESR1 (0x1C) bit D4 (checksum error).
4.2.2.9

Channel 1 Control Register 2 (CH1_CNTRL2)

- address:
- data width:
- access mode:
- reset value:
Bit Description
0 reset/delete channel1 transmit and acknowledge section
1 reset/delete channel1 receive section
2 reset protocol unit
7:3 always '0' / reserved
Note: The above bits must be specifically set/cleared as required. There is no automatic reset.
See also the procedure following disconnect described in chapter 3.4.
SMCS332SpW
User Manual
1
C
1
CS
Figure Checksum generation
= 0x00000 + 0xFF + 0 = 0x000FF
= 0x000FF + 0xFF + 0 = 0x001FE
= 0x0FE01 + 0xFF + 0 = 0x0FF00
= 0x0FF00 + 0xFF + 0 = 0x0FFFF
= 0x0FFFF + 0xFF + 0 = 0x100FE
= 0x100FE + 0xFF + 1 = 0x101FE
0x19
3 bit, D2:0
read / write
0x00
– All Rights Reserved – Copyright per DIN 34 –
DATA
8
+
17
+
16
17
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue: 1.4
Updated: 9-Sep-2006
Page: 34 of 131