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7 Signal Description
The Figure below shows the SMCS332SpW embedded in a typical module environment:
SMCS332SpW
HOSTBIGE
BOOTLINK
RESET
CLK
CLK10
4
SPACEWIRE LINK 1
4
SPACEWIRE LINK 2
4
SPACEWIRE LINK 3
TIME_CODE_SYNC
5
JTAG
This section describes the pins of the SMCS. Groups of pins represent busses where the highest number is the MSB.
O = Output; I = Input; Z = High Impedance
O/Z = if using a configuration with two SMCS332SpWs these signals can directly be connected together (WIROR)
(*) = active low signal
Signal Name
Type Function
HSEL*
HRD*
HWR*
HADR(7:0)
HDATA(31:0)
I/O/Z SMCS data
HACK
O/Z host acknowledge. SMCS deasserts this output to add wait
HINTR*
SMCSADR(3:0)
SMCSID(3:0)
HOSTBIGE
SMCS332SpW
User Manual
HINTR
HSEL
HRD
HWR
HACK
HDATA
8
HADR
4
SMCSADR
4
SMCSID
ID
CPUR
4
SES
CMCS0
CMCS1
CMRD
CMWR
32
CMDATA
16
CMADR
VCC
CAM
COCO
COCI
GND
PLLOUT
I
Select host interface
I
host interface read strobe
I
host interface write strobe
I
SMCS register address lines. This address lines will be
used to access (address) the SMCS registers.
states to a SMCS access. After SMCS is ready this output
will be asserted.
O
host interrupt request line
I
SMCS Address. The binary value of this lines will be
compared with the value of the SMCS ID lines.
I
SMCS ID lines: offers possibility to use sixteen SMCS
within one HSEL*
I
0:
host I/F Little Endian
– All Rights Reserved – Copyright per DIN 34 –
32
SELECT A
SELECT B
SELECT A
OE A
SELECT B
OE B
OE A
WE A
OE B
WE B
WE A
DATA A
DATA B
WE B
DATA A
ADDR A
DATA B
ADDR B
ADDR A
ADDR B
Dual Port
Communication
Dual Port
Memory
Communication
BANK 0
Memory
BANK 1
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
64 of 131
Processor
INTERRUPT IN
CHIP SELECTS
READ
WRITE
WAIT/ACK
DATA
ADDRESS
max. output
load [pF]
current [mA]
3
50
3
50
3
50
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