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Bit
Description
received acknowledge packet has a wrong checksum (only, when generate checksum enabled, bit 4 of register
CH1_CNTRL1).
4
in transparent mode:
checksum error (if checksum enabled)
5
in transparent mode:
wrong route - destination byte (if routing enabled) (destination byte not equal with CH1_ADDR or
CH2_RT_ADDR or CH3_RT_ADDR)
7:6
always '0' / reserved
4.2.2.13
Channel 1 Error Source Register 2 (CH1_ESR2)
- address:
- data width:
- access mode:
- reset value:
Only in protocol mode:
The CH1_ESR2 register give detailed information about the source of the channel 1error interrupt (bit 1/byte 0 of the
interrupt status register ISR).
The channel 1 error source register 2 is readable and the bits are reset only by writing '1', thus ensuring status never gets
missed by software.
Bit
Description
0
Simple Interprocessor Command (SIC) sequence error. That means: the SMCS332SpW received an unexpected
acknowledge packet.
1
Received SIC packet with a wrong checksum (only, when generate checksum enabled, bit 4 of register
CH1_CNTRL1).
2
received SIC packet has a wrong control byte
3
received SIC packet has a wrong destination byte (not equal with register CH1_ADDR)
4
the received SIC command/control byte was not enabled (see also bit 0 in register CH1_PR_STAR)
5
received data packet has a wrong destination byte (not equal with register CH1_ADDR)
6
received data packet has a wrong checksum (generate checksum enabled, bit4 of register CH1_CNTRL1)
7
always '0' / reserved
4.2.2.14
Channel 1 COMI Configuration Register (CH1_COMICFG)
- address:
- data width:
- access mode:
- reset value:
SMCS332SpW
User Manual
0x1D
7 bit, D6:0
read / write
0x00
0x1F
8 bit, D7:0
read / write
0x00
– All Rights Reserved – Copyright per DIN 34 –
EADS Astrium GmbH, ASE2
Doc No: SMCS_ASTD_UM_100
Issue:
1.4
Updated: 9-Sep-2006
Page:
36 of 131
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